EP2AGX125EF35I3N Altera Corporation, EP2AGX125EF35I3N Datasheet - Page 79

• Manufacturer Part Number: EP2AGX125EF35I3N
• Description: IC ARRIA II GX 125K 1152FBGA
• Manufacturer: Altera Corporation
• Series: Arria II GXr

Specifications of EP2AGX125EF35I3N

• Number Of Logic Elements/cells: 118143
• Number Of Labs/clbs: 4964
• Total Ram Bits: 8315904
• Number Of I /o: 452
• Number Of Gates: -
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-BBGA
• Lead Free Status: Lead free
• Rohs Status: RoHS Compliant

Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–63. Memory Output Clock Jitter Specification for Arria II GZ Devices
December 2011 Altera Corporation
Clock period jitter
Cycle-to-cycle period jitter
Duty cycle jitter
Clock period jitter
Cycle-to-cycle period jitter
Duty cycle jitter
Notes to
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
(2) The clock jitter specification applies to memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a
(3) The memory output clock jitter stated in
PLL output routed on a regional or global clock network as specified. Altera recommends using regional clock networks whenever possible.
Table
Parameter
1–63:
Table 1–63
Duty Cycle Distortion (DCD) Specifications
Table 1–64
Table 1–64. Duty Cycle Distortion on I/O Pins for Arria II GX Devices
Table 1–65
Table 1–65. Duty Cycle Distortion on I/O Pins for Arria II GZ Devices
Output Duty Cycle
Note to
(1) The DCD specification applies to clock outputs from the PLL, global clock tree, IOE driving dedicated, and general
Output Duty Cycle
Note to
(1) The DCD specification applies to clock outputs from the PLL, global clock tree, IOE driving dedicated, and general
purpose I/O pins.
purpose I/O pins.
Table
Table
Symbol
Symbol
Regional
Regional
Network
Regional
Global
Global
Global
Clock
lists the memory output clock jitter specifications for Arria II GZ devices.
lists the worst-case DCD specifications for Arria II GX devices.
lists the worst-case DCD specifications for Arria II GZ devices.
1–64:
1–65:
Table 1–63
is applicable when an input jitter of 30 ps is applied.
Symbol
t
t
t
t
t
t
JIT(duty)
JIT(duty)
JIT(per)
JIT(per)
JIT(cc)
JIT(cc)
Min
45
Min
45
C4
C3, I3
Max
55
-82.5
-82.5
-110
-165
Min
-55
-90
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
Max
55
Min
45
I3, C5, I5
–3
Max
82.5
82.5
110
165
55
90
Max
(Note
55
Min
45
1), (2),
Min
C4, I4
45
-82.5
-82.5
-110
-165
Min
-55
-90
(Note 1)
C6
(Note 1)
(3)
Max
55
Max
55
–4
82.5
82.5
Max
110
165
55
90
Unit
%
Unit
%
Unit
ps
ps
ps
ps
ps
ps
1–71