EP2AGX260EF29I5 Altera Corporation, EP2AGX260EF29I5 Datasheet - Page 38

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EP2AGX260EF29I5

Manufacturer Part Number
EP2AGX260EF29I5
Description
IC ARRIA II GX FPGA 260K 780FBGA
Manufacturer
Altera Corporation
Series
Arria II GXr
Datasheet

Specifications of EP2AGX260EF29I5

Number Of Logic Elements/cells
244188
Number Of Labs/clbs
10260
Total Ram Bits
12038144
Number Of I /o
372
Number Of Gates
-
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-BBGA
Lead Free Status
Contains lead
Rohs Status
RoHS non-compliant

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0
1–30
Table 1–35. Transceiver Specifications for Arria II GZ Devices (Part 3 of 5)
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
Receiver DC Coupling
Support
Differential on-chip
termination resistors
Differential and common
mode return loss
Programmable PPM
detector
Run length
Programmable equalization
t
t
t
t
Receiver CDR
3 dB Bandwidth in
lock-to-data (LTD) mode
Receiver buffer and CDR
offset cancellation time (per
channel)
Programmable DC gain
LTR
LTR_LTD_Manual
LTD_Manual
LTD_Auto
(10)
Description
(13)
(9)
Symbol/
(12)
(11)
DC Gain Setting = 0
DC Gain Setting = 1
DC Gain Setting = 2
SRIO 3.125 Gbps
PCIe (Gen 1 and
(OIF) CEI PHY at
SRIO 1.25 Gbps
SRIO 2.5 Gbps
100 setting
120 setting
150- setting
85 setting
SONET OC12
SONET OC48
SRIO SR/LR,
CPRI LV/HV,
6.375 Gbps
Conditions
CEI SR/LR,
PCIe Gen1
PCIe Gen2
Gen 2),
HiGig+,
OBSAI,
XAUI,
SATA
XAUI
GIGE
For more information about receiver DC coupling support, refer to the
“DC-Coupled Links” section in the
Devices
Min
15
–C3 and –I3
chapter.
± 62.5, 100, 125, 200, 250, 300, 500, 1,000
100 ± 20%
120 ± 20%
150 ± 20%
85 ± 20%
Typ
0
3
6
(1)
17000
4000
4000
Max
200
16
75
Compliant
2.0 - 3.5
40 - 65
20 - 35
10 - 18
10 - 18
10 - 18
14 - 19
6 - 10
6 - 10
3 - 6
Chapter 1: Device Datasheet for Arria II Devices
Min
Transceiver Architecture for Arria II
15
–C4 and –I4
100 ± 20%
120 ± 20%
150 ± 20%
December 2011 Altera Corporation
85 ± 20%
Typ
0
3
6
Switching Characteristics
17000
4000
4000
Max
200
16
75
recon
cycles
fig_
ppm
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
clk
dB
µs
µs
dB
dB
dB
UI
ns
ns

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