EP4SGX530HH35I3N Altera Corporation, EP4SGX530HH35I3N Datasheet - Page 72

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EP4SGX530HH35I3N

Manufacturer Part Number
EP4SGX530HH35I3N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera Corporation
Series
Stratix® IV GXr
Datasheet

Specifications of EP4SGX530HH35I3N

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
28033024
Number Of I /o
564
Number Of Gates
-
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1152-BBGA Exposed Pad
Lead Free Status
Lead free
Rohs Status
RoHS Compliant

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Part Number:
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1–64
Table 1–53. Glossary Table (Part 2 of 4)
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
M, N, O
Letter
K, L,
P
Q
R
J
J
JTAG Timing
Specifications
PLL
Specifications
R
L
Subject
High-speed I/O block: Deserialization factor (width of parallel data bus).
JTAG Timing Specifications:
Diagram of PLL Specifications
Note:
(1) Core Clock can only be fed by dedicated clock input pins or PLL outputs.
Receiver differential input discrete resistor (external to Stratix IV device).
TMS
TDO
TCK
TDI
Core Clock
Key
CLK
Reconfigurable in User Mode
t
JCH
t
JPZX
t
JCP
t
JCL
Switchover
f
IN
External Feedback
N
t
JPCO
f
INPFD
(1)
t
JPSU
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
PFD
M
Definitions
CP
t
LF
JPH
VCO
f
VCO
t
JPXZ
Counters
C0..C9
December 2011 Altera Corporation
CLKOUT Pins
f
f
OUT_EXT
OUT
GCLK
RCLK
Glossary

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