STM32F051C4 STMicroelectronics, STM32F051C4 Datasheet - Page 12

• Manufacturer Part Number: STM32F051C4
• Description: Entry-level ARM Cortex-M0 MCU with 16 Kbytes Flash, 48 MHz CPU, motor control and CEC functions
• Manufacturer: STMicroelectronics

Specifications of STM32F051C4

• Voltage Range: 2.0 V to 3.6 V
• Conversion Range: 0 to 3.6V
• Systick Timer: 24-bit downcounter

Functional overview
3.7
3.8
3.9
3.9.1
3.9.2
12/22
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.
Boot modes
At startup, the boot pin and boot selector option bit are used to select one of three boot
options:
●
●
●
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1.
Power management
Power supply schemes
●
●
●
For more details on how to connect power pins, refer to
Power supply supervisors
The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
V
●
●
POR/PDR
Boot from User Flash
Boot from System Memory
Boot from embedded SRAM
V
Provided externally through V
V
(minimum voltage to be applied to V
The V
must be provided first.
V
registers (through power switch) when V
The POR monitors only the V
that V
The PDR monitors both the V
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that V
equal to V
DD
DDA
BAT
= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
, without the need for an external reset circuit.
= 1.6 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
= 2.0 to 3.6 V: external analog power supply for ADC, Reset blocks, RCs and PLL
DDA
DDA
DD
should arrive first and be greater than or equal to V
voltage level must be always greater or equal to the V
.
Doc ID 018746 Rev 2
DD
DD
DD
supply voltage. During the startup phase it is required
and V
pins.
DDA
DDA
DD
is 2.4 V when the ADC and DAC are used).
supply voltages, however the V
is not present.
Figure 9: Power supply
DD
DDA
.
DD
voltage level and
is higher than or
STM32F051x
DDA
scheme.
power