STM32F100VC STMicroelectronics, STM32F100VC Datasheet - Page 13

• Manufacturer Part Number: STM32F100VC
• Description: Mainstream value line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 24 MHz CPU, motor control and CEC functions
• Manufacturer: STMicroelectronics

Specifications of STM32F100VC

• Peripherals Supported: timers, ADC, SPIs, I2Cs, USARTs and DACs
• Conversion Range: 0 to 3.6 V
• One 16-bit, 6-channel Advanced-control Timer: up to 6 channels for PWM output, dead time generation and emergency stop
• Systick Timer: 24-bit downcounter

STM32F100xC, STM32F100xD, STM32F100xE
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
Overview
ARM
The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F100xx value line family having an embedded ARM core, is therefore
compatible with all ARM tools and software.
Embedded Flash memory
Up to 512 Kbytes of embedded Flash memory is available for storing programs and data.
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
Embedded SRAM
Up to 32 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
FSMC (flexible static memory controller)
The FSMC is embedded in the high-density value line family. It has four Chip Select outputs
supporting the following modes: SRAM, PSRAM, and NOR.
Functionality overview:
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LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
The three FSMC interrupt lines are ORed in order to be connected to the NVIC
No read FIFO
Code execution from external memory
No boot capability
The targeted frequency is HCLK/2, so external access is at 12 MHz when HCLK is at
24 MHz
®
Cortex™-M3 core with embedded Flash and SRAM
Doc ID 15081 Rev 5
Description
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