STM32F101T4 STMicroelectronics, STM32F101T4 Datasheet - Page 25

• Manufacturer Part Number: STM32F101T4
• Description: Mainstream Access line, ARM Cortex-M3 MCU with 16 Kbytes Flash, 36 MHz CPU
• Manufacturer: STMicroelectronics

Specifications of STM32F101T4

• Core: ARM 32-bit Cortex™-M3 CPU
• Peripherals Supported: timers, ADC, SPIs, I2Cs and USARTs
• Conversion Range: 0 to 3.6 V
• Systick Timer: 24-bit downcounter

STM32F101x4, STM32F101x6
Table 4.
1. I = input, O = output, S = supply.
2. FT= 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
8. The pins number 2 and 3 in the VFQFPN36 package, and 5 and 6 in the LQFP48 and LQFP64 packages are configured as
40
41
42
43
44
45
46
47
48
number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be
called SPI, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum
load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available
from the STMicroelectronics website: www.st.com.
OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For
more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.
Pins
56
57
58
59
60
61
62
63
64
31
32
33
34
35
36
1
-
-
Low-density STM32F101xx pin definitions (continued)
Pin name
BOOT0
V
V
PB4
PB5
PB6
PB7
PB8
PB9
DD_3
SS_3
I/O
I/O
I/O
I/O
I/O
I/O
S
S
I
Doc ID 15058 Rev 5
FT
FT
FT
FT
FT
(after reset)
function
NJTRST
BOOT0
V
V
Main
PB5
PB6
PB7
PB8
PB9
DD_3
SS_3
(3)
Table 2 on page
I2C_SDA
I2C_SCL
I2C_SMBA
Default
Alternate functions
Pinouts and pin description
11.
(7)
(7)
TIM3_CH1 / PB4
USART1_RX
USART1_TX
TIM3_CH2 /
(3)(4)
SPI_MISO
SPI_MOSI
I2C_SCL
I2C_SDA
Remap
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