STM8S207RB

Manufacturer Part NumberSTM8S207RB
DescriptionPerformance line, 24 MHz STM8S 8-bit MCU, up to 128 Kbytes Flash, integrated EEPROM
ManufacturerSTMicroelectronics
STM8S207RB datasheet
 

Specifications of STM8S207RB

Max Fcpuup to 24 MHz, 0 wait states @ fCPU≤ 16 MHzProgramup to 128 Kbytes Flash; data retention 20 years at 55 °C after 10 kcycles
Dataup to 2 Kbytes true data EEPROM; endurance 300 kcyclesRamup to 6 Kbytes
Advanced Control Timer16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization  
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
Page 1/103

Download datasheet (2Mb)Embed
Next
Performance line, 24 MHz STM8S 8-bit MCU, up to 128 KB Flash,
integrated EEPROM, 10-bit ADC, timers, 2 UARTs, SPI, I²C, CAN
Features
Core
– Max f
: up to 24 MHz, 0 wait states @
CPU
f
16 MHz
CPU
– Advanced STM8 core with Harvard
architecture and 3-stage pipeline
– Extended instruction set
– Max 20 MIPS @ 24 MHz
Memories
– Program: up to 128 Kbytes Flash; data
retention 20 years at 55 °C after 10 kcycles
– Data: up to 2 Kbytes true data EEPROM;
endurance 300 kcycles
– RAM: up to 6 Kbytes
Clock, reset and supply management
– 2.95 to 5.5 V operating voltage
– Low power crystal resonator oscillator
– External clock input
– Internal, user-trimmable 16 MHz RC
– Internal low power 128 kHz RC
– Clock security system with clock monitor
– Wait, active-halt, & halt low power modes
– Peripheral clocks switched off individually
– Permanently active, low consumption
power-on and power-down reset
Interrupt management
– Nested interrupt controller with 32
interrupts
– Up to 37 external interrupts on 6 vectors
Timers
– 2x 16-bit general purpose timers, with 2+3
CAPCOM channels (IC, OC or PWM)
– Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-
time insertion and flexible synchronization
– 8-bit basic timer with 8-bit prescaler
– Auto wakeup timer
– Window watchdog, independent watchdog
February 2012
LQFP80 14x14
LQFP48 7x7
Communications interfaces
– High speed 1 Mbit/s active beCAN 2.0B
– UART with clock output for synchronous
operation - LIN master mode
– UART with LIN 2.1 compliant, master/slave
modes and automatic resynchronization
– SPI interface up to 10 Mbit/s
2
– I
C interface up to 400 Kbit/s
10-bit ADC with up to 16 channels
I/Os
– Up to 68 I/Os on an 80-pin package
including 18 high sink outputs
– Highly robust I/O design, immune against
current injection
– Development support
– Single wire interface module (SWIM) and
debug module (DM)
96-bit unique ID key for each device
Table 1.
Device summary
Part numbers: STM8S207xx
STM8S207MB, STM8S207M8, STM8S207RB,
STM8S207R8, STM8S207R6, STM8S207CB,
STM8S207C8, STM8S207C6, STM8S207SB,
STM8S207S8, STM8S207S6, STM8S207K8
STM8S207K6
Part numbers: STM8S208xx
STM8S208MB, STM8S208M8, STM8S208RB,
STM8S208R8, STM8S208R6, STM8S208CB,
STM8S208C8, STM8S208C6, STM8S208SB,
STM8S208S8, STM8S208S6
Doc ID 14733 Rev 12
STM8S207xx
STM8S208xx
LQFP64 14x14
LQFP64 10x10
LQFP44 10x10
LQFP32 7x7
1/103
www.st.com
1

STM8S207RB Summary of contents

  • Page 1

    ... Single wire interface module (SWIM) and debug module (DM) ■ 96-bit unique ID key for each device Table 1. Device summary Part numbers: STM8S207xx STM8S207MB, STM8S207M8, STM8S207RB, STM8S207R8, STM8S207R6, STM8S207CB, STM8S207C8, STM8S207C6, STM8S207SB, STM8S207S8, STM8S207S6, STM8S207K8 STM8S207K6 Part numbers: STM8S208xx STM8S208MB, STM8S208M8, STM8S208RB, ...

  • Page 2

    Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 3

    STM8S207xx, STM8S208xx 6.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 4

    Contents 12 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 5

    STM8S207xx, STM8S208xx List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 6

    List of tables Table 49. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 7

    STM8S207xx, STM8S208xx List of figures Figure 1. STM8S20xxx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 8

    List of figures Figure 49. STM8S207xx/208xx performance line ordering information scheme 8/103 Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx ( ...

  • Page 9

    STM8S207xx, STM8S208xx 1 Introduction This datasheet contains the description of the STM8S20xxx performance line features, pinout, electrical characteristics, mechanical data and ordering information. ● For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S ...

  • Page 10

    Description 2 Description The STM8S20xxx performance line 8-bit microcontrollers offer from 32 to 128 Kbytes Flash program memory. They are referred to as high-density devices in the STM8S microcontroller family reference manual. All devices of the STM8S20xxx performance line provide ...

  • Page 11

    ... STM8S207xx, STM8S208xx Table 2. STM8S20xxx performance line features Device STM8S207MB STM8S207M8 STM8S207RB STM8S207R8 STM8S207R6 STM8S207CB STM8S207C8 STM8S207C6 STM8S207SB STM8S207S8 STM8S207S6 STM8S207K8 STM8S207K6 STM8S208MB STM8S208RB STM8S208R8 STM8S208R6 STM8S208CB STM8S208C8 STM8S208C6 STM8S208SB STM8S208S8 STM8S208S6 ...

  • Page 12

    Block diagram 3 Block diagram Figure 1. STM8S20xxx performance line block diagram Reset Single wire debug interf. 400 Kbit/s 10 Mbit/s LIN master SPI emul. Master/slave autosynchro 1 Mbit/s 16 channels 1/2/4 kHz beep 1. Legend: ADC: Analog-to-digital converter beCAN: ...

  • Page 13

    STM8S207xx, STM8S208xx 4 Product overview The following section intends to give an overview of the basic features of the STM8S20xxx performance line functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). 4.1 ...

  • Page 14

    Product overview 4.2 Single wire interface module (SWIM) and debug module (DM) The single wire interface module and debug module permits non-intrusive, real-time in- circuit debugging and fast memory programming. SWIM Single wire interface module for direct access to the ...

  • Page 15

    STM8S207xx, STM8S208xx The size of the UBC is programmable through the UBC option byte increments of 1 page (512 bytes) by programming the UBC option byte in ICP mode. This divides the program memory into two areas: ● Main program ...

  • Page 16

    Product overview 4.5 Clock controller The clock controller distributes the system clock (f to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. Features ● Clock prescaler: To get the best ...

  • Page 17

    STM8S207xx, STM8S208xx 4.6 Power management For efficent power management, the application can be put in one of four different low-power modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available ...

  • Page 18

    Product overview Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in ...

  • Page 19

    STM8S207xx, STM8S208xx 4.12 TIM4 - 8-bit basic timer ● 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128 ● Clock source: CPU clock ● Interrupt source overflow/update Table 4. TIM timer features Counter ...

  • Page 20

    Product overview 4.14.1 UART1 Main features ● One Mbit/s full duplex SCI ● SPI emulation ● High precision baud rate generator ● Smartcard emulation ● IrDA SIR encoder decoder ● LIN master mode ● Single wire half duplex mode Asynchronous ...

  • Page 21

    STM8S207xx, STM8S208xx Asynchronous communication (UART mode) ● Full duplex communication - NRZ standard format (mark/space) ● Programmable transmit and receive baud rates Mbit/s (f following any standard baud rate regardless of the input frequency ● Separate enable ...

  • Page 22

    Product overview 2 4.14 ● master features: – Clock generation – Start and stop generation ● slave features: – Programmable I – Stop bit detection ● Generation and detection of 7-bit/10-bit addressing ...

  • Page 23

    STM8S207xx, STM8S208xx 5 Pinouts and pin description 5.1 Package pinouts Figure 3. LQFP 80-pin pinout OSCIN/PA1 OSCOUT/PA2 [TIM3_CH1] TIM2_CH3/PA3 UART1_RX/ (HS) PA4 UART1_TX/ (HS) PA5 UART1_CK/ (HS) PA6 (HS) PH0 ( AIN15/PF7 AIN14/PF6 AIN13/PF5 AIN12/PF4 1. (HS) high sink capability. ...

  • Page 24

    Pinouts and pin description Figure 4. LQFP 64-pin pinout [TIM3_CH1] TIM2_CH3/PA3 UART1_RX/ (HS) PA4 UART1_TX/ (HS) PA5 UART1_CK/ (HS) PA6 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode alternate ...

  • Page 25

    STM8S207xx, STM8S208xx Figure 5. LQFP 48-pin pinout [TIM3_CH1] TIM2_CH3/PA3 UART1_RX/(HS) PA4 UART1_TX/(HS) PA5 UART1_CK/(HS) PA6 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode alternate function remapping option (If the ...

  • Page 26

    Pinouts and pin description Figure 6. LQFP 44-pin pinout 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode alternate function remapping option (If the same alternate function is shown twice, ...

  • Page 27

    STM8S207xx, STM8S208xx Figure 7. LQFP 32-pin pinout 1. (HS) high sink capability alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function ...

  • Page 28

    Pinouts and pin description Table 5. Legend/abbreviations for pinout table Type Level Output speed Port and control configuration Reset state Table 6. Pin description Pin number Pin name NRST PA1/OSCIN ...

  • Page 29

    STM8S207xx, STM8S208xx Table 6. Pin description (continued) Pin number Pin name PH3 PF7/AIN15 PF6/AIN14 PF5/AIN13 ...

  • Page 30

    Pinouts and pin description Table 6. Pin description (continued) Pin number Pin name PH4/TIM1_ETR PH5/ TIM1_CH3N I PH6/ TIM1_CH2N I ...

  • Page 31

    STM8S207xx, STM8S208xx Table 6. Pin description (continued) Pin number Pin name PG2 PG3 PG4 PI0 ...

  • Page 32

    Pinouts and pin description Table 6. Pin description (continued) Pin number Pin name PD6 UART3_RX PD7/TLI 1. The default state of UART1_RX and UART3_RX pins is controlled by the ROM ...

  • Page 33

    STM8S207xx, STM8S208xx 6 Memory and register map 6.1 Memory map Figure 8. Memory map 0x00 0000 RAM ( Kbytes) 1024 bytes stack 0x 00 17FF 0x 00 1800 Reserved 0x 00 3FFF 0x 00 4000 ...

  • Page 34

    Memory and register map Table 7 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address in each case. Table 7. Flash, Data EEPROM and RAM boundary addresses Memory area Flash ...

  • Page 35

    STM8S207xx, STM8S208xx Table 8. I/O port hardware register map (continued) Address Block 0x00 500F 0x00 5010 0x00 5011 Port D 0x00 5012 0x00 5013 0x00 5014 0x00 5015 0x00 5016 Port E 0x00 5017 0x00 5018 0x00 5019 0x00 501A ...

  • Page 36

    Memory and register map Table 9. General hardware register map Address Block 0x00 5050 to 0x00 5059 0x00 505A 0x00 505B 0x00 505C Flash 0x00 505D 0x00 505E 0x00 505F 0x00 5060 to 0x00 5061 0x00 5062 Flash 0x00 5063 ...

  • Page 37

    STM8S207xx, STM8S208xx Table 9. General hardware register map (continued) Address Block 0x00 50CC CLK 0x00 50CD 0x00 50CE to 0x00 50D0 0x00 50D1 WWDG 0x00 50D2 0x00 50D3 to 0x00 50DF 0x00 50E0 0x00 50E1 IWDG 0x00 50E2 0x00 50E3 ...

  • Page 38

    Memory and register map Table 9. General hardware register map (continued) Address Block 0x00 5216 0x00 5217 0x00 5218 0x00 5219 0x00 521A 0x00 521B 0x00 521C 0x00 521D 0x00 521E to 0x00 522F 0x00 5230 0x00 ...

  • Page 39

    STM8S207xx, STM8S208xx Table 9. General hardware register map (continued) Address Block 0x00 5250 0x00 5251 0x00 5252 0x00 5253 0x00 5254 0x00 5255 0x00 5256 0x00 5257 0x00 5258 0x00 5259 0x00 525A 0x00 525B 0x00 525C 0x00 525D 0x00 ...

  • Page 40

    Memory and register map Table 9. General hardware register map (continued) Address Block 0x00 5300 0x00 5301 0x00 5302 0x00 5303 0x00 5304 0x00 5305 0x00 5306 0x00 5307 0x00 5308 0x00 5309 0x00 530A TIM2 0x00 530B 00 530C0x ...

  • Page 41

    STM8S207xx, STM8S208xx Table 9. General hardware register map (continued) Address Block 0x00 532B 0x00 532C 0x00 532D TIM3 0x00 532E 0x00 532F 0x00 5330 0x00 5331 to 0x00 533F 0x00 5340 0x00 5341 0x00 5342 0x00 5343 TIM4 0x00 5344 ...

  • Page 42

    Memory and register map Table 9. General hardware register map (continued) Address Block 0x00 5428 0x00 5429 0x00 542A 0x00 542B 0x00 542C 0x00 542D 0x00 542E 0x00 542F beCAN 0x00 5430 0x00 5431 0x00 5432 0x00 5433 0x00 5434 ...

  • Page 43

    STM8S207xx, STM8S208xx Table 10. CPU/SWIM/debug module/interrupt controller registers Address Block Register Label 0x00 7F00 0x00 7F01 0x00 7F02 0x00 7F03 0x00 7F04 (1) 0x00 7F05 CPU 0x00 7F06 0x00 7F07 0x00 7F08 0x00 7F09 0x00 7F0A 0x00 7F0B to 0x00 ...

  • Page 44

    Memory and register map Table 10. CPU/SWIM/debug module/interrupt controller registers (continued) Address Block Register Label 0x00 7F98 0x00 7F99 DM 0x00 7F9A DM_ENFCTR 0x00 7F9B to 0x00 7F9F 1. Accessible by debug module only 2. Product dependent value, see Figure ...

  • Page 45

    STM8S207xx, STM8S208xx 7 Interrupt vector mapping Table 11. Interrupt mapping IRQ Source Description no. block RESET Reset TRAP Software interrupt 0 TLI External top level interrupt 1 AWU Auto wake up from halt 2 CLK Clock controller 3 EXTI0 Port ...

  • Page 46

    Option bytes 8 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each ...

  • Page 47

    STM8S207xx, STM8S208xx Table 13. Option byte description Option byte no. OPT0 OPT1 OPT2 Description ROP[7:0] Memory readout protection (ROP) 0xAA: Enable readout protection (write access via SWIM protocol) Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory ...

  • Page 48

    Option bytes Table 13. Option byte description (continued) Option byte no. OPT3 OPT4 OPT5 OPT6 OPT7 48/103 Description LSI_EN: Low speed internal clock enable 0: LSI clock is not available as CPU clock source 1: LSI clock is available as ...

  • Page 49

    STM8S207xx, STM8S208xx Table 13. Option byte description (continued) Option byte no. OPTBL Description BL[7:0] Bootloader option byte For STM8S products, this option is checked by the boot ROM code after reset. Depending on the content of addresses 0x487E, 0x487F, and ...

  • Page 50

    Unique ID 9 Unique ID The devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the ...

  • Page 51

    STM8S207xx, STM8S208xx 10 Electrical characteristics 10.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 10.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...

  • Page 52

    Electrical characteristics 10.1.5 Pin loading conditions 10.1.6 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 10. Pin loading conditions 10.1.7 Pin input voltage The input voltage measurement on a pin of the device is ...

  • Page 53

    STM8S207xx, STM8S208xx 10.2 Absolute maximum ratings Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure ...

  • Page 54

    Electrical characteristics Table 16. Current characteristics Symbol I Total current into V VDD I Total current out of V VSS Output current sunk by any I/O and control pin I IO Output current source by any I/Os and control pin ...

  • Page 55

    STM8S207xx, STM8S208xx 10.3 Operating conditions The device must be used in operating conditions that respect the parameters in addition, full account must be taken of all physical capacitor characteristics and tolerances. Table 18. General operating conditions Symbol f Internal CPU ...

  • Page 56

    Electrical characteristics Figure 12. f CPUmax FUNCTIONALITY NOT GUARANTEED IN THIS AREA Table 19. Operating conditions at power-up/power-down Symbol VDD V DD Reset release t TEMP delay Power-on reset V IT+ threshold Brown-out reset V IT- threshold ...

  • Page 57

    STM8S207xx, STM8S208xx 10.3.2 Supply current characteristics The current consumption is measured as described in Total current consumption in run mode The MCU is placed under the following conditions: ● All I/O pins in input mode with a static value at ...

  • Page 58

    Electrical characteristics Table 21. Total current consumption with code execution in run mode at V Symbol Parameter CPU ≤ T 105 °C A Supply CPU current in run mode, code executed ...

  • Page 59

    STM8S207xx, STM8S208xx Total current consumption in wait mode Table 22. Total current consumption in wait mode at V Symbol Parameter CPU ≤ T 105 ° Supply CPU I current in DD(WFI) wait mode ...

  • Page 60

    Electrical characteristics Total current consumption in active halt mode Table 24. Total current consumption in active halt mode at V Main voltage Symbol Parameter regulator (MVR) Supply current in I DD(AH) active halt mode 1. Data based on characterization results, ...

  • Page 61

    STM8S207xx, STM8S208xx Total current consumption in halt mode Table 26. Total current consumption in halt mode at V Symbol Parameter Supply current in halt I DD(H) mode Table 27. Total current consumption in halt mode at V Symbol Parameter I ...

  • Page 62

    Electrical characteristics Total current consumption and timing in forced reset state Table 29. Total current consumption and timing in forced reset state Symbol Parameter I Supply current in reset state DD(R) Reset release to bootloader vector t RESETBL fetch 1. ...

  • Page 63

    STM8S207xx, STM8S208xx Current consumption curves Figure 14 and Figure 15 RAM. Figure 14. Typ. I Figure 15. Typ. I show typical current consumption measured with code executing HSI RC osc, f DD(RUN 3.5 3 ...

  • Page 64

    Electrical characteristics 10.3.3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for V Table 31. HSE user external clock characteristics Symbol User external clock source f HSE_ext frequency OSCIN input pin high level ...

  • Page 65

    STM8S207xx, STM8S208xx Table 32. HSE oscillator characteristics Symbol Parameter External high speed oscillator f HSE frequency R Feedback resistor F (1) C Recommended load capacitance I HSE oscillator power consumption DD(HSE) g Oscillator transconductance m (4) t Startup time SU(HSE) ...

  • Page 66

    Electrical characteristics 10.3.4 Internal clock sources and timing characteristics Subject to general operating conditions for V High speed internal RC oscillator (HSI) Table 33. HSI oscillator characteristics Symbol Parameter f Frequency HSI Accuracy of HSI oscillator ACC HSI Accuracy of ...

  • Page 67

    STM8S207xx, STM8S208xx Low speed internal RC oscillator (LSI) Subject to general operating conditions for V Table 34. LSI oscillator characteristics Symbol f Frequency LSI t LSI oscillator wakeup time su(LSI) I LSI oscillator power consumption DD(LSI) 1. Guaranteeed by design, ...

  • Page 68

    Electrical characteristics 10.3.5 Memory characteristics RAM and hardware registers Table 35. RAM and hardware registers Symbol Minimum supply voltage without losing data stored in RAM (in halt mode or under reset hardware registers (only in ...

  • Page 69

    STM8S207xx, STM8S208xx 10.3.6 I/O port pin characteristics General characteristics Subject to general operating conditions for V unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down ...

  • Page 70

    Electrical characteristics Figure 20. Typical V Figure 21. Typical pull-up resistance vs V Figure 22. Typical pull-up current The pull- pure resistor (slope goes through 0). 70/103 and temperatures IL ...

  • Page 71

    STM8S207xx, STM8S208xx Table 38. Output driving current (standard ports) Symbol Parameter Output low level with 8 pins sunk V OL Output low level with 4 pins sunk Output high level with 8 pins sourced V OH Output high level with ...

  • Page 72

    Electrical characteristics Typical output level curves Figure 24 to Figure 31 pin. Figure 23. Typ. V Figure 24. Typ. V Figure 25. Typ. V 72/103 show typical output level curves measured with output on a single @ ...

  • Page 73

    STM8S207xx, STM8S208xx Figure 26. Typ. V Figure 27. Typ. V Figure 28. Typ 3.3 V (true open drain ports -40˚C 2 25˚C 1.75 85˚C 125˚C 1.5 1.25 1 0.75 0.5 0. ...

  • Page 74

    Electrical characteristics Figure 29. Typ. V Figure 30. Typ. V Figure 31. Typ. V 74/103 (standard ports -40˚C 2 25˚C 1.75 85˚C 125˚C 1.5 1.25 1 0.75 0.5 0.25 0 ...

  • Page 75

    STM8S207xx, STM8S208xx Figure 32. Typ. V 10.3.7 Reset pin characteristics Subject to general operating conditions for V Table 41. NRST pin characteristics Symbol Parameter V NRST Input low level voltage IL(NRST) V NRST Input high level voltage IH(NRST) V NRST ...

  • Page 76

    Electrical characteristics Figure 34. Typical NRST pull-up resistance vs V Figure 35. Typical NRST pull-up current vs V The reset network shown in must ensure that the level on the NRST pin can go below the V Table 41. Otherwise ...

  • Page 77

    STM8S207xx, STM8S208xx SPI serial peripheral interface 10.3.8 Unless otherwise specified, the parameters given in performed under ambient temperature, f conditions. t MASTER Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). ...

  • Page 78

    Electrical characteristics Figure 37. SPI timing diagram - slave mode and CPHA = 0 NSS input t SU(NSS) CPHA= 0 CPOL=0 t w(SCKH) CPHA w(SCKL) CPOL=1 t a(SO) MISO OUT su(SI) MOSI I NPUT Figure ...

  • Page 79

    STM8S207xx, STM8S208xx Figure 39. SPI timing diagram - master mode High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 t su(MI) MISO INP UT MOSI OUTUT 1. Measurement points are done at CMOS levels: 0.3 V ...

  • Page 80

    Electrical characteristics 2 10.3 interface characteristics 2 Table 43 characteristics Symbol t SCL clock low time w(SCLL) t SCL clock high time w(SCLH) t SDA setup time su(SDA) t SDA data hold time h(SDA) t r(SDA) ...

  • Page 81

    STM8S207xx, STM8S208xx Figure 40. Typical application with I 1. Measurement points are made at CMOS levels: 0 bus and timing diagram and 0 Doc ID 14733 Rev 12 Electrical characteristics 81/103 ...

  • Page 82

    Electrical characteristics 10.3.10 10-bit ADC characteristics Subject to general operating conditions for V specified. Table 44. ADC characteristics Symbol f ADC clock frequency ADC V Analog supply DDA V Positive reference voltage REF+ V Negative reference voltage REF- V Conversion ...

  • Page 83

    STM8S207xx, STM8S208xx Table 45. ADC accuracy with R Symbol |E | Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error L 1. Data based ...

  • Page 84

    Electrical characteristics Figure 41. ADC accuracy characteristics 1. Example of an actual transfer curve. 2. The ideal transfer curve 3. End point correlation line E = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves. T ...

  • Page 85

    STM8S207xx, STM8S208xx 10.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until ...

  • Page 86

    Electrical characteristics Electromagnetic interference (EMI) Emission tests conform to the SAE IEC 61967-2 standard for test software, board layout and pin loading. Table 48. EMI data Symbol Parameter General conditions = Peak level = 25 °C ...

  • Page 87

    ... Symbol LU Static latch-up class 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard). Parameter = 25 ° ...

  • Page 88

    Package characteristics 11 Package characteristics To meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at www.st.com. ECOPACK® ...

  • Page 89

    STM8S207xx, STM8S208xx 11.1 Package mechanical data 11.1.1 LQFP package mechanical data Figure 43. 80-pin low profile quad flat package ( Pin 1 identification 1 Table 51. 80-pin low profile quad flat package mechanical data ...

  • Page 90

    Package characteristics Figure 44. 64-pin low profile quad flat package ( Pin 1 identification 1 Table 52. 64-pin low profile quad flat package mechanical data (14 x 14) Symbol ...

  • Page 91

    STM8S207xx, STM8S208xx Figure 45. 64-pin low profile quad flat package ( Pin 1 identification 1 Table 53. 64-pin low profile quad flat package mechanical data (10 x 10) Symbol ...

  • Page 92

    Package characteristics Figure 46. 48-pin low profile quad flat package ( Pin 1 identification 1 Table 54. 48-pin low profile quad flat package mechanical data Symbol ...

  • Page 93

    STM8S207xx, STM8S208xx Figure 47. 44-pin low profile quad flat package ( Pin 1 identification 1 Table 55. 44-pin low profile quad flat package mechanical data Symbol 11.800 D1 ...

  • Page 94

    Package characteristics Figure 48. 32-pin low profile quad flat package ( Pin 1 identification Table 56. 32-pin low profile quad flat package mechanical data Symbol ...

  • Page 95

    STM8S207xx, STM8S208xx 11.2 Thermal characteristics The maximum chip junction temperature (T Table 18: General operating conditions on page The maximum chip-junction temperature, T using the following equation Jmax Amax Where: is the maximum ambient temperature ...

  • Page 96

    Package characteristics 11.2.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order code (see Figure 49: STM8S207xx/208xx performance line ordering information scheme(1) on page 99). The following example shows how to calculate ...

  • Page 97

    ... In addition, STM8 application development is supported by a low-cost in-circuit debugger/programmer. The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application ...

  • Page 98

    ... Software tools STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8. A free version that outputs Kbytes of code is available ...

  • Page 99

    STM8S207xx, STM8S208xx 13 Ordering information Figure 49. STM8S207xx/208xx performance line ordering information scheme Example: Product class STM8 microcontroller Family type S = Standard Sub-family type 208 = Full peripheral set 207 = Intermediate peripheral set Pin count ...

  • Page 100

    Revision history 14 Revision history Table 58. Document revision history Date 23-May-2008 05-Jun-2008 22-Jun-2008 12-Aug-2008 20-Oct-2008 08-Dec-2008 30-Jan-2009 10-Jul-2009 100/103 Revision 1 Initial release. Added part numbers on page 1 and in 2 Updated Section 4: Product Updated Section 10: ...

  • Page 101

    STM8S207xx, STM8S208xx Table 58. Document revision history (continued) Date 10-Jul-2009 13-Apr-2010 Revision Section 10: Electrical updated Table 15: Voltage characteristics operating conditions; updated VCAP specifications in Section 10.3.1: VCAP external replaced Figure 19; updated 8 updated Figure 22 and cont’d ...

  • Page 102

    Revision history Table 58. Document revision history (continued) Date 14-Sep-2010 22-Mar-2011 10-Feb-2012 102/103 Revision Added part number STM8S208M8 to Updated "reset state" of table. Added footnote 4 to Table 6: Pin Table 9: General hardware register values; updated the reset ...

  • Page 103

    ... STM8S207xx, STM8S208xx Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...