ST7263BH2 STMicroelectronics, ST7263BH2 Datasheet - Page 92

• Manufacturer Part Number: ST7263BH2
• Description: LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 32K FLASH/ROM, DFU CAPABILITY, 8-BIT ADC, WDG, TIMER, SCI and I2C
• Manufacturer: STMicroelectronics

Specifications of ST7263BH2

• 4, 8, 16 Or 32 Kbytes Program Memory: high density Flash (HDFlash), FastROM or ROM with Read-Out and Write protection

On-chip peripherals
92/186
Control register 1 (SCICR1)
Reset value: x000 0000 (x0h)
R8
7
7 R8 Receive data bit 8.
6 T8 Transmit data bit 8.
5 SCID Disabled for low power consumption
4 M Word length.
3 WAKE Wakeup method.
2 PCE Parity control enable.
1 PS Parity selection.
0 PIE Parity interrupt enable.
T8
This bit is used to store the 9th bit of the received word when M=1.
This bit is used to store the 9th bit of the transmitted word when M=1.
When this bit is set the SCI prescalers and outputs are stopped and the end of the
current byte transfer in order to reduce power consumption.This bit is set and
cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
This bit determines the word length. It is set or cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Note: The M bit must not be modified during a data transfer (both transmission
This bit determines the SCI wakeup method, it is set or cleared by software.
0: Idle Line
1: Address Mark
This bit selects the hardware parity control (generation and detection). When the
parity control is enabled, the computed parity is inserted at the MSB position (9th
bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set
and cleared by software. Once it is set, PCE is active after the current byte (in
reception and in transmission).
0: Parity control disabled
1: Parity control enabled
This bit selects the odd or even parity when the parity generation/detection is
enabled (PCE bit set). It is set and cleared by software. The parity will be selected
after the current byte.
0: Even parity
1: Odd parity
This bit enables the interrupt capability of the hardware parity control when a parity
error is detected (PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
1: Parity error interrupt enabled.
and reception).
SCID
Doc ID 7516 Rev 8
M
Read/write
WAKE
PCE
PS
ST7263Bxx
PIE
0