ST7263BK2 STMicroelectronics, ST7263BK2 Datasheet - Page 160

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ST7263BK2

Manufacturer Part Number
ST7263BK2
Description
LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 32K FLASH/ROM, DFU CAPABILITY, 8-BIT ADC, WDG, TIMER, SCI and I2C
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST7263BK2

4, 8, 16 Or 32 Kbytes Program Memory
high density Flash (HDFlash), FastROM or ROM with Read-Out and Write protection

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Electrical characteristics
13.10.3
160/186
I
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDAI and SCLI).
The ST7 I
described in the following table.
Subject to general operating conditions for V
Table 76.
1. Data based on standard I
2. At 4 MHz f
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low
4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
2
Symbol
t
t
t
t
t
t
w(SCLH)
w(STO:S
w(SCLL)
t
su(SDA)
t
t
su(STO)
C interface
t
t
t
su(STA)
h(SDA)
r(SDA)
r(SCL)
f(SDA)
h(STA)
f(SCL)
approximately 260 KHz.
period of SCL signal.
undefined region of the falling edge of SCL.
TA)
C
b
2
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
Repeated START condition setup time
STOP condition setup time
STOP to START condition time (bus free)
Capacitive load for each bus line
C interface meets the requirements of the standard I
CPU
I
2
C characteristics
, max.I
2
C speed (400 kHz) is not achievable. In this case, max. I
Parameter
2
C protocol requirement, not tested in production.
Doc ID 7516 Rev 8
DD
, f
OSC
Standard mode
Min
250
0
4.7
4.0
4.0
4.7
4.0
4.7
(3)
-
-
-
, and T
I
2
C
(1)
1000
Max
300
400
A
-
-
-
-
-
-
-
-
unless otherwise specified.
2
C communication protocol
Fast mode I
20+0.1C
20+0.1C
2
C speed will be
Min
100
0
1.3
0.6
0.6
0.6
0.6
1.3
(4)
-
b
b
2
900
Max
C
300
300
400
ST7263Bxx
(1)(2)
-
-
-
-
-
-
-
(3)
Unit
pF
µs
ns
µs
µs
µs

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