ST92150CV1Q-Auto STMicroelectronics, ST92150CV1Q-Auto Datasheet - Page 149

• Manufacturer Part Number: ST92150CV1Q-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST92150CV1Q-Auto

• Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM)
• Minimum Instruction Time: 83 ns (24 MHz int. clock)

EXTERNAL MEMORY INTERFACE REGISTERS (Cont’d)
EXTERNAL MEMORY REGISTER 2 (EMR2)
R246 - Read/Write
Register Page: 21
Reset value: 0001 1111 (1Fh)
Bit 7 = Reserved.
Bit 6 = ENCSR: Enable Code Segment Register.
This bit affects the ST9 CPU behavior whenever
an interrupt request is issued.
0: The CPU works in original ST9 compatibility
1: If ENCSR is set, ISR is only used to point to the
7
-
mode concerning stack frame during interrupts.
For the duration of the interrupt service routine,
ISR is used instead of CSR, and the interrupt
stack frame is identical to that of the original
ST9: only the PC and Flags are pushed. This
avoids saving the CSR on the stack in the event
of an interrupt, thus ensuring a faster interrupt
response time. The drawback is that it is not
possible for an interrupt service routine to per-
form inter-segment calls or jumps: these instruc-
tions would update the CSR, which, in this case,
is not used (ISR is used instead). The code seg-
ment size for all interrupt service routines is thus
limited to 64K bytes.
interrupt vector table and to initialize the CSR at
the beginning of the interrupt service routine: the
old CSR is pushed onto the stack together with
the PC and flags, and CSR is then loaded with
ENCSR DPRREM MEMSEL LAS1 LAS0 UAS1 UAS0
0
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Bit 5 = DPRREM: Data Page Registers remapping
0: The locations of the four MMU (Memory Man-
1: The four MMU Data Page Registers are
Refer to
Bit 4 = MEMSEL: Memory Selection.
Warning: Must be kept at 1.
Bit 3:2 = LAS[1:0]: Lower memory address strobe
stretch.
These two bits contain the number of wait cycles
(from 0 to 3) to add to the System Clock to stretch
AS during external lower memory block accesses
(A21=”0”). The reset value is 3.
the contents of ISR. In this case, iret will also re-
store CSR from the stack. This approach allows
interrupt service routines to access the entire
4Mbytes of address space; the drawback is that
the interrupt response time is slightly increased,
because of the need to also save CSR on the
stack. Full compatibility with the original ST9 is
lost in this case, because the interrupt stack
frame is different; this difference, however,
should not affect the vast majority of programs.
agement Unit) Data Page Registers (DPR0,
DPR1, DPR2 and DPR3) are in page 21.
swapped with that of the Data Registers of ports
0-3.
Figure 73
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