ST6209C STMicroelectronics, ST6209C Datasheet
ST6209C
Specifications of ST6209C
Related parts for ST6209C
ST6209C Summary of contents
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... Bit manipulation Development Tools ■ – Full hardware/software development package ST6209C 8MHz Max -40°C to +125°C PDIP20/SO20/SSOP20 Rev 4 ST6208C ST6209C ST6210C ST6220C PDIP20 SO20 SSOP20 CDIP20W Section 11.5 for Ordering Information) ST6210C ST6220C 1/104 1 ...
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INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... ST6208C/ST6209C/ST6210C/ST6220C 1 INTRODUCTION The ST6208C, 09C, 10C and 20C devices are low cost members of the ST62xx 8-bit HCMOS family of microcontrollers, which is targeted at low to me- dium complexity applications. All ST62xx devices are based on a building block approach: a com- mon core is surrounded by a number of on-chip peripherals ...
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... PB7/Ain* I/O 9 PB6/Ain* I/O 10 PB5/Ain* I/O 11 PB4/Ain* I/O 12 PB3/Ain* I/O 13 PB2/Ain* I/O 14 PB1/Ain* I/O 15 PB0/Ain* I/O 16 PA3/ 20mA Sink I/O 17 PA2/ 20mA Sink I/O 18 PA1/ 20mA Sink I/O ST6208C/ST6209C/ST6210C/ST6220C TIMER 2 19 OSCin 3 18 it1 OSCout 4 17 NMI RESET it2 Ain*/PB7 Ain*/PB6 9 it2 Ain*/PB5 ...
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... ST6208C/ST6209C/ST6210C/ST6220C Pin n° Pin Name 19 PA0/ 20mA Sink I Legend / Abbreviations for Table * Depending on device. Please refer input output supply, IPU = input with pull-up The input with pull-up configuration (reset state) is valid as long as the user software does not change it. ...
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... INTERRUPT & RESET VECTORS 0FFFh ST6208C/ST6209C/ST6210C/ST6220C Briefly, Program space contains user program code in OTP and user vectors; Data space con- tains user data in RAM and in OTP, and Stack space accommodates six levels of stack for sub- routine and interrupt service routine nesting. ...
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... ST6208C/ST6209C/ST6210C/ST6220C MEMORY MAP (Cont’d) Figure 4. Program Memory Map ST6208C, 09C 0000h NOT IMPLEMENTED 0AFFh 0B00h * RESERVED 0B9Fh 0BA0h USER PROGRAM MEMORY 1024 BYTES 0F9Fh 0FA0h * RESERVED 0FEFh 0FF0h INTERRUPT VECTORS 0FF7h 0FF8h * RESERVED 0FFBh 0FFCh NMI VECTOR 0FFDh 0FFEh USER RESET VECTOR ...
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... Data Space accommodates all the data necessary for processing the user program. This space com- prises the RAM resource, the processor core and peripheral registers, as well as read-only data ST6208C/ST6209C/ST6210C/ST6220C such as constants and look-up tables in OTP/ EPROM. 3.1.4.1 Data ROM All read-only data is physically stored in program memory, which also accommodates the Program Space ...
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... ST6208C/ST6209C/ST6210C/ST6220C MEMORY MAP (Cont’d) Table 2. Hardware Register Map Register Address Block Label 080h CPU X,Y,V,W to 083h 0C0h DRA I/O Ports 0C1h DRB 0C2h 0C3h 0C4h DDRA I/O Ports 0C5h DDRB 0C6h 0C7h 0C8h CPU IOR 0C9h ROM DRWR 0CAh 0CBh 0CCh ORA I/O Ports ...
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... PROGRAM SPACE 0000h 64-BYTE ROM 0FFFh ST6208C/ST6209C/ST6210C/ST6220C 3.1.6.1 Data ROM Window Register (DRWR) The DRWR can be addressed like any RAM loca- tion in the Data Space. This register is used to select the 64-byte block of program memory to be read in the Data ROM win- dow (from address 40h to address 7Fh in Data space) ...
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... ST6208C/ST6209C/ST6210C/ST6220C MEMORY MAP (Cont’d) 3.1.6.2 Data ROM Window memory addressing In cases where some data (look-up tables for ex- ample) are stored in program memory, reading these data requires the use of the Data ROM win- dow mechanism this: 1. The DRWR register has to be loaded with the 64-byte block number where the data are located (in program memory) ...
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... NMI Interrupt Vector 0FFEh-0FFFh Note: OTP/EPROM devices can be programmed with the development tools available from ST6208C/ST6209C/ST6210C/ST6220C STMicroelectronics (please refer to page pin. The 3.2.2 EPROM Erasing PP The EPROM devices can be erased by exposure to Ultra Violet light. The characteristics of the MCU ...
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... ST6208C/ST6209C/ST6210C/ST6220C 3.3 OPTION BYTES Each device is available for production in user pro- grammable versions (OTP) as well as in factory coded versions (ROM). OTP devices are shipped to customers with a default content (00h), while ROM factory coded parts contain the code sup- plied by the customer. This implies that OTP de- ...
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... RESET VALUE = xxh 7 RESET VALUE = xxh 11 RESET VALUE = RESET VECTOR @ 0FFEh-0FFFh ST6208C/ST6209C/ST6210C/ST6220C tions. The accumulator can be addressed in Data Space as a RAM location at address FFh. Thus the ST6 can manipulate the accumulator just like any other register in Data Space. Index Registers (X, Y). These two registers are used in Indirect addressing mode as pointers to memory locations in Data Space ...
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... ST6208C/ST6209C/ST6210C/ST6220C CPU REGISTERS (Cont’d) The 12-bit length allows the direct addressing of 4096 bytes in Program Space. However, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program ROM Page register. The PC value is incremented after reading the ad- dress of the current instruction ...
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... Figure 9. Clock Circuit Block Diagram f OSC MAIN OSCILLATOR OSG ENABLE OPTION BIT (See OPTION BYTE SECTION) ST6208C/ST6209C/ST6210C/ST6220C Table 6 figurations using an external crystal or ceramic resonator, an external clock input, an external re- sistor (R the LFAO. For more details on configuring the clock options, refer to the Option Bytes section of this document. ...
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... ST6208C/ST6209C/ST6210C/ST6220C CLOCK SYSTEM (Cont’d) 5.1.1 Main Oscillator The oscillator configuration is specified by select- ing the appropriate option in the option bytes (refer to the Option Bytes section of this document). When the CRYSTAL/RESONATOR option is se- lected, it must be used with a quartz crystal, a ce- ramic resonator or an external signal provided on the OSCin pin ...
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... Figure 11. LFAO Oscillator Function MAIN OSCILLATOR STOPS f OSC f LFAO f INT ST6208C/ST6209C/ST6210C/ST6220C imum internal clock frequency which is supply voltage dependent. OSG 5.1.2.2 Variations Over-frequency given power supply level, is seen by the OSG as spikes; it therefore filters out some cycles in order that the internal clock fre- ...
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... ST6208C/ST6209C/ST6210C/ST6220C CLOCK SYSTEM (Cont’d) 5.1.3 Low Frequency Auxiliary Oscillator (LFAO) The Low Frequency Auxiliary Oscillator has three main purposes. Firstly, it can be used to reduce power consumption in non timing critical routines. Secondly, it offers a fully integrated system clock, without any external components. Lastly, it acts as a backup oscillator in case of main oscillator fail- ure ...
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... IT+ to avoid a parasitic reset when the MCU starts run- ning and sinks current on the supply (hysteresis). Figure 12. Low Voltage Detector Reset IT+ V IT- RESET ST6208C/ST6209C/ST6210C/ST6220C The LVD Reset circuitry generates a reset when V is below: DD – V when V is rising DD IT+ – V ...
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... ST6208C/ST6209C/ST6210C/ST6220C 5.3 RESET 5.3.1 Introduction The MCU can be reset in three ways: A low pulse input on the RESET pin ■ Internal Watchdog reset ■ Internal Low Voltage Detector (LVD) reset ■ 5.3.2 RESET Sequence The basic RESET sequence consists of 3 main phases: Internal (watchdog or LVD) or external Reset ■ ...
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... Reset state as long as the RESET pin is held low. Figure 14. Reset Block Diagram RESET 1) Resistive ESD protection. ST6208C/ST6209C/ST6210C/ST6220C If the RESET pin is grounded while the MCU is in RUN or WAIT modes, processing of the user pro- gram is stopped (RUN mode only), the I/O ports are configured as inputs with pull-up resistors and the main oscillator is restarted ...
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... ST6208C/ST6209C/ST6210C/ST6220C RESET (Cont’d) 5.3.4 Watchdog Reset The MCU provides a Watchdog timer function in order to be able to recover from software hang- ups. If the Watchdog register is not refreshed be- fore an end-of-count condition is reached, a Watchdog reset is generated. After a Watchdog reset, the MCU restarts in the same way Reset was generated by the RE- SET pin ...
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... WITH INTERRUPT” CONFIGURATION TIMER (TSCR REGISTER) A/D CONVERTER * (ADCR REGISTER) * Depending on device. See device summary on page 1. ST6208C/ST6209C/ST6210C/ST6220C struction to the associated interrupt service rou- tine. When an interrupt source generates an interrupt 18. request, the PC register is loaded with the address of the interrupt vector, which then causes a Jump to the relevant interrupt service routine, thus serv- icing the interrupt ...
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... ST6208C/ST6209C/ST6210C/ST6220C 5.5 INTERRUPT RULES MANAGEMENT A Reset can interrupt the NMI and peripheral ■ interrupt routines The Non Maskable Interrupt request has the ■ highest priority and can interrupt any peripheral interrupt routine at any time but cannot interrupt another NMI interrupt. No peripheral interrupt can interrupt another. If ■ ...
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... ESB bit in the IOR register), an interrupt is latched although a rising edge may not have oc- cured on the associated pin. ST6208C/ST6209C/ST6210C/ST6220C This is due to the vector #2 circuitry.The worka- round is to discard this first interrupt request in the routine (using a flag for example). ...
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... ST6208C/ST6209C/ST6210C/ST6220C 5.10 INTERRUPT HANDLING PROCEDURE The interrupt procedure is very similar to a call pro- cedure, in fact the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know the context and the time at which it occurred re- sult, the user should save all Data space registers which may be used within the interrupt routines ...
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... Vector #3 TIMER Timer underflow Vector #4 ADC* End Of Conversion * Depending on device. See device summary on page 1. ST6208C/ST6209C/ST6210C/ST6220C 1: Low level sensitive mode is selected for inter- rupt vector #1 Bit 5 = ESB Edge Selection bit Falling edge mode on interrupt vector #2 1: Rising edge mode on interrupt vector #2 ...
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... ST6208C/ST6209C/ST6210C/ST6220C 6 POWER SAVING MODES 6.1 INTRODUCTION To give a large measure of flexibility to the applica- tion in terms of power consumption, two main pow- er saving modes are implemented in the ST6 (see Figure 19). In addition, the Low Frequency Auxiliary Oscillator (LFAO) can be used instead of the main oscillator to reduce power consumption in RUN and WAIT modes ...
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... A peripheral interrupt (timer, ADC,...), – An external interrupt (I/O port, NMI) The Program Counter then branches to the start- ing address of the interrupt or RESET service rou- tine. Refer to Figure 20. See also Section 6.4.1. ST6208C/ST6209C/ST6210C/ST6220C Figure 20. WAIT Mode Flowchart OSCILLATOR Clock to PERIPHERALS WAIT INSTRUCTION Clock to CPU N N INTERRUPT Y ...
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... ST6208C/ST6209C/ST6210C/ST6220C 6.3 STOP MODE STOP mode is the lowest power consumption mode of the MCU (see Figure The MCU goes into STOP mode as soon as the STOP instruction is executed. This has the follow- ing effects: – Program execution is stopped, the microcontrol- ler can be considered as being “frozen”. ...
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... EXCTNL is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from STOP mode (such as external interrupt). Refer to the Interrupt Mapping table for more details. ST6208C/ST6209C/ST6210C/ST6220C STOP INSTRUCTION 1 LEVEL ...
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... ST6208C/ST6209C/ST6210C/ST6220C 6.4 NOTES RELATED TO WAIT AND STOP MODES 6.4.1 Exit from Wait and Stop Modes 6.4.1.1 NMI Interrupt It should be noted that when the GEN bit in the IOR register is low (interrupts disabled), the NMI interrupt is active but cannot cause a wake up from STOP/WAIT modes. 6.4.1.2 Restart Sequence ...
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... I/O pin. Different input modes can be selected by software through the DR and OR registers, see External Interrupt Function ST6208C/ST6209C/ST6210C/ST6220C All input lines can be individually connected by software to the interrupt system by programming the OR and DR registers accordingly. The inter- rupt trigger modes (falling edge, rising edge and low level) can be configured by software for each port as described in the Interrupt section ...
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... ST6208C/ST6209C/ST6210C/ST6220C I/O PORTS (Cont’d) Figure 23. I/O Port Block Diagram RESET ST6 INTERNAL BUS TO INTERRUPT * TO ADC * Depending on device. See device summary on page 1. Table 9. I/O Port Configurations DDR Note Don’t care 38/104 1 PULL-UP DATA ...
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... Output Open Drain Output Push-pull Note *. xxx = DDR, OR, DR Bits respectively ST6208C/ST6209C/ST6210C/ST6220C 2. Handling Unused Port Bits On ports that have less than 8 external pins con- nected: – Leave the unbonded pins in reset state and do not change their configuration. – Do not use instructions that act on a whole port register (INC, DEC, or read operations) ...
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... ST6208C/ST6209C/ST6210C/ST6220C I/O PORTS (Cont’d) Table 10. I/O Port Option Selections MODE AVAILABLE ON Input DDRx ORx DRx Reset state Input with pull up DDRx ORx DRx Input with pull up with interrupt DDRx ORx DRx Analog Input DDRx ORx DRx Open drain output (5mA) ...
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... DDRA MSB 0C5h DDRB 0CCh ORA MSB 0CDh ORB ST6208C/ST6209C/ST6210C/ST6220C Bits 7:0 = DD[7:0] Data direction register bits. The DDR register gives the input/output direction configuration of the pins. Each bit is set and cleared by software. 0: Input mode 1: Output mode OPTION REGISTER (OR) 0 Port x Option Register ORx with ...
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... ST6208C/ST6209C/ST6210C/ST6220C 8 ON-CHIP PERIPHERALS 8.1 WATCHDOG TIMER (WDG) 8.1.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. The Watchdog cir- cuit generates an MCU reset on expiry of a pro- grammed time period, unless the program refresh- es the counter’ ...
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... ST62xx devices, and should be used wherever possible. Watchdog related options should be selected on the basis of a trade-off between application security and STOP ST6208C/ST6209C/ST6210C/ST6220C mode availability (refer to the description of the WDACT and EXTCNTL bits on the Option Bytes). When STOP mode is not required, hardware acti- ...
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... ST6208C/ST6209C/ST6210C/ST6220C WATCHDOG TIMER (Cont’d) These instructions test the C bit and reset the MCU (i.e. disable the Watchdog) if the bit is set (i.e. if the Watchdog is active), thus disabling the Watchdog. For more information on the use of the watchdog, please read application note AN1015. 8.1.5 Low Power Modes ...
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... C bit is set. When (Watchdog de- activated) the SR bit is the MSB of the 7-bit timer. 0: Generate (write software reset generated, MSB of 7-bit timer ST6208C/ST6209C/ST6210C/ST6220C Bit Watchdog Control bit. If the hardware option is selected (WDACT bit in Option byte), this bit is forced high and cannot be changed by the user (the Watchdog is always ac- tive) ...
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... ST6208C/ST6209C/ST6210C/ST6220C 8.2 8-BIT TIMER 8.2.1 Introduction The 8-Bit Timer on-chip peripheral is a free run- ning downcounter based on an 8-bit downcounter with a 7-bit programmable prescaler, giving a max- 15 imum count The peripheral may be config- ured in three different operating modes. Figure 27. Timer Block Diagram TIMER ...
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... Initialize) bit in the TSCR register. When PSI is re- set, the counter is frozen and the prescaler is load- ed with the value 7Fh. When PSI is set, the pres- ST6208C/ST6209C/ST6210C/ST6220C caler and the counter run at the rate of the select- ed clock source. Counter and Prescaler Initialization After RESET, the counter and the prescaler are in- itialized to 0FFh and 7Fh respectively ...
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... ST6208C/ST6209C/ST6210C/ST6220C 8-BIT TIMER (Cont’d) 8.2.4 Functional Description There are three operating modes, which are se- lected by the TOUT and DOUT bits (see TSCR register). These three modes correspond to the two clocks which can be connected to the 7-bit prescaler (f ÷ TIMER pin signal), and to INT the output mode ...
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... The TMZ bit can be tested under program control to perform a timer function whenever it goes high and has to be cleared by the user. The low-to-high TMZ ST6208C/ST6209C/ST6210C/ST6220C bit transition is used to latch the DOUT bit in the TSCR and, if the TOUT bit is set, DOUT is trans- ferred to the TIMER pin ...
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... ST6208C/ST6209C/ST6210C/ST6220C 8-BIT TIMER (Cont’d) 8.2.5 Low Power Modes Mode Description No effect on timer. WAIT Timer interrupt events cause the device to exit from WAIT mode. Timer registers are frozen except in Event STOP Counter mode (with external clock on TIM- ER pin). 50/104 1 8.2.6 Interrupts Event Enable ...
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... Reset Value TCR 0D3h Reset Value TSCR 0D4h Reset Value ST6208C/ST6209C/ST6210C/ST6220C ETI=0 the timer interrupt is disabled. If ETI=1 and TMZ=1 an interrupt request is generated. 0: Interrupt disabled (reset state) 1: Interrupt enabled 0 Bit 5 = TOUT Timer Output Control. When low, this bit selects the input mode for the ...
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... ST6208C/ST6209C/ST6210C/ST6220C 8.3 A/D CONVERTER (ADC) 8.3.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 8-bit, successive approximation con- verter. This peripheral has multiplexed analog in- put channels (refer to device pin out description) that allow the peripheral to convert the analog volt- age levels from different sources. ...
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... Caution: Only one I/O line must be configured as an analog input at any time. The user must avoid any situation in which more than one I/O pin is se- lected as an analog input simultaneously, because they will be shorted internally. ST6208C/ST6209C/ST6210C/ST6220C 8.3.3.4 Software Procedure Refer to the Control register (ADCR) and Data reg- ister (ADR) in and V pins ...
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... ST6208C/ST6209C/ST6210C/ST6220C A/D CONVERTER (Cont’d) 8.3.4 Recommendations The following six notes provide additional informa- tion on using the A/D converter. 1.The A/D converter does not feature a sample and hold circuit. The analog voltage to be meas- ured should therefore be stable during the entire conversion cycle. Voltage variation should not ex- ceed ± ...
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... ADCR EAI 0D1h Reset Value 0 ST6208C/ST6209C/ST6210C/ST6220C cally cleared when the STA bit is set. Data in the data conversion register are valid only when this bit is set to “1”. 0: Conversion is not complete 1: Conversion can be read from the ADR register Bit 5 = STA: Start of Conversion. Write Only. ...
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... ST6208C/ST6209C/ST6210C/ST6220C 9 INSTRUCTION SET 9.1 ST6 ARCHITECTURE The ST6 architecture has been designed for max- imum efficiency while keeping byte usage to a minimum; in short, to provide byte-efficient pro- gramming. The ST6 core has the ability to set or clear any register or RAM location bit in Data space using a single instruction. Furthermore, pro- grams can branch to a selected address depend- ing on the status of any bit in Data space ...
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... Data space register Δ Affected * Not Affected ST6208C/ST6209C/ST6210C/ST6220C Load & Store. These instructions use one, two or three bytes depending on the addressing mode. For LOAD, one operand is the Accumulator and the other operand is obtained from data memory using one of the addressing modes. ...
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... ST6208C/ST6209C/ST6210C/ST6220C INSTRUCTION SET (Cont’d) Arithmetic and Logic. These instructions are used to perform arithmetic calculations and logic operations. In AND, ADD, CP, SUB instructions one operand is always the accumulator while, de- pending on the addressing mode, the other can be Table 18. Arithmetic & Logic Instructions Instruction ...
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... Extended JP abc Extended Notes: abc 12-bit address * Not Affected ST6208C/ST6209C/ST6210C/ST6220C Control Instructions. Control instructions control microcontroller operations during program execu- tion. Jump and Call. These two instructions are used to perform long (12-bit) jumps or subroutine calls to any location in the whole program space. ...
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... ST6208C/ST6209C/ST6210C/ST6220C Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6 LOW 0 1 0000 0001 HI 2 JRNZ 4 CALL abc 0000 1 pcr 2 ext 1 2 JRNZ 4 CALL abc 0001 1 pcr 2 ext 1 2 JRNZ 4 CALL abc ...
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... Abbreviations for Addressing Modes: Legend: dir Direct sd Short Direct imm Immediate inh Inherent ext Extended b.d Bit Direct bt Bit Test pcr Program Counter Relative ind Indirect ST6208C/ST6209C/ST6210C/ST6220C 1010 1011 1100 JRNC 4 RES 2 JRZ 4 e b0,rr e pcr 2 b.d 1 pcr 3 JRNC 4 SET 2 JRZ 4 e ...
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... ST6208C/ST6209C/ST6210C/ST6220C 10 ELECTRICAL CHARACTERISTICS 10.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- ferred 10.1.1 Minimum and Maximum Values Unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the ...
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... Pure digital pins must have a negative injection less than 1mA. In addition recommended to inject the current as far as possible from the analog input pins. ST6208C/ST6209C/ST6210C/ST6220C tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability ...
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... ST6208C/ST6209C/ST6210C/ST6220C 10.3 OPERATING CONDITIONS 10.3.1 General Operating Conditions Symbol Parameter V Supply voltage DD f Oscillator frequency OSC V Operating Supply Voltage DD T Ambient temperature range A Notes oscillator frequency above 1.2MHz is recommended for reliable A/D results. 2. Operating conditions with T =-40 to +125°C. A Figure 38. f Maximum Operating Frequency Versus V ...
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... RESET IN THIS AREA 4 0 2.5 3 Figure 40. Typical LVD Thresholds Versus Temperature for OTP devices Thresholds [V] 4.2 4 3.8 3.6 -40°C 25°C T [°C] ST6208C/ST6209C/ST6210C/ST6220C , f , and T DD OSC A Conditions V -V IT+ IT- 3) Not detected by the LVD DD =25°C. They are given only as design guidelines and are not tested. A ...
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... ST6208C/ST6209C/ST6210C/ST6220C 10.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST6 functional operating modes over tempera- ture range does not take into account the clock source current consumption. To get the total de- 10.4.1 RUN Modes Symbol Parameter Supply current in RUN mode (see Figure 42 & ...
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... Notes: 1. Typical data are based on T =25° Data based on characterization results, tested in production All I/O pins in input with pull-up mode (no load), all peripherals in reset state; clock input (OSC square wave, OSG and LVD disabled. ST6208C/ST6209C/ST6210C/ST6220C Conditions f =32kHz OSC 3) f =1MHz ...
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... ST6208C/ST6209C/ST6210C/ST6220C SUPPLY CURRENT CHARACTERISTICS (Cont’d) Figure 44. Typical I in WAIT programmed IDD [µA] 800 8MHz 1M 700 4MHz 32KHz 2MHz 600 500 400 300 200 100 VDD [V] Figure 45. Typical I in WAIT programmed to 00H IDD [µA] 120 8MHz 1M 4MHz 32KHz ...
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... Figure 46. Typical I in WAIT IDD [µA] 600 8MHz 1M 4MHz 32KHz 500 2MHz 400 300 200 100 VDD [V] ST6208C/ST6209C/ST6210C/ST6220C and Temperature for ROM devices CPU IDD [µA] 450 400 350 300 250 200 150 100 5 6 -20 8MHz 1MHz 4MHz 32KHz ...
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... ST6208C/ST6209C/ST6210C/ST6220C SUPPLY CURRENT CHARACTERISTICS (Cont’d) 10.4.3 STOP Mode Symbol Parameter Supply current in STOP mode I DD (see Figure 47 & Figure Notes: 1. Typical data are based on V =5. All I/O pins in input with pull-up mode (no load), all peripherals in reset state, OSG and LVD disabled, option bytes programmed to 00H. Data based on characterization results, tested in production Maximum STOP consumption for -40° ...
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... Data based on a differential Data based on a differential Data based on a differential Data based on a differential I DD ST6208C/ST6209C/ST6210C/ST6220C source current consumption. To get the total de- vice consumption, the two current values must be added (except for STOP mode). Conditions f =32 kHz, OSC ...
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... ST6208C/ST6209C/ST6210C/ST6220C 10.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for V 10.5.1 General Timings Symbol Parameter t Instruction cycle time c(INST) Interrupt reaction time t = Δt v(IT v(IT) c(INST) 10.5.2 External Clock Source Symbol Parameter V OSC input pin high level voltage OSCINH IN V OSC input pin low level voltage ...
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... The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R Refer to crystal/ceramic resonator manufacturer for more details. Figure 50. Typical Application with a Crystal or Ceramic Resonator C L1 RESONATOR C L2 ST6208C/ST6209C/ST6210C/ST6220C characterization results with specified typical ex- ternal components. Refer to the crystal/ceramic resonator manufacturer for more details (frequen- cy, package, accuracy...). f OSC f ...
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... ST6208C/ST6209C/ST6210C/ST6220C CLOCK AND TIMING CHARACTERISTICS (Cont’d) 10.5.4 RC Oscillator The ST6 internal clock can be supplied with an external RC oscillator. Depending on the accuracy of the frequency is about 20 may not be suitable for some applications. Symbol Parameter f RC oscillator frequency OSC R RC Oscillator external resistor NET Notes: 1 ...
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... Oscillator Safeguard (OSG) and Low Frequency Auxiliary Oscillator (LFAO) Symbol Parameter Low Frequency Auxiliary Oscillator f 1) LFAO Frequency Internal Frequency with OSG ena- f OSG bled Figure 54. Typical LFAO Frequencies Note: 1. Data based on characterization results. ST6208C/ST6209C/ST6210C/ST6220C Figure 53. Typical RC Oscillator frequency vs. Temperature (V fosc [MHz Conditions =25° =5.0 V ...
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... ST6208C/ST6209C/ST6210C/ST6220C 10.6 MEMORY CHARACTERISTICS Subject to general operating conditions for V 10.6.1 RAM and Hardware Registers Symbol Parameter 1) V Data retention RM 10.6.2 EPROM Program Memory Symbol Parameter 2) t Data retention ret Figure 55. EPROM Retention Time vs. Temperature Retention time [Years] 100000 10000 1000 100 10 1 0.1 -40 -30 -20 -10 Notes: 1 ...
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... RESET, OSCx pin characteristics). Figure 56. EMC Recommended Star Network Power Supply Connection POWER SUPPLY SOURCE ST6208C/ST6209C/ST6210C/ST6220C ESD: Electro-Static Discharge (positive and ■ negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. ...
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... ST6208C/ST6209C/ST6210C/ST6220C EMC CHARACTERISTICS (Cont’d) 10.7.2 Absolute Electrical Sensitivity Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, re- fer to the AN1181 application note. 10.7.2.1 Electro-Static Discharge (ESD) Electro-Static Discharges (3 positive then 3 nega- ...
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... CH =150pF C S ESD 2) GENERATOR ST6208C/ST6209C/ST6210C/ST6220C DLU: Electro-Static Discharges (one positive ■ then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode ...
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... ST6208C/ST6209C/ST6210C/ST6220C EMC CHARACTERISTICS (Cont’d) 10.7.3 ESD Pin Protection Strategy To protect an integrated circuit against Electro- Static Discharge the stress must be controlled to prevent degradation or destruction of the circuit el- ements. The stress generally affects the circuit el- ements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress ...
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... Data based on characterization results, not tested in production generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source. Figure 62. Two typical Applications with unused I/O Pin V DD 10kΩ ST6208C/ST6209C/ST6210C/ST6220C , f , and T DD OSC Conditions 2) 2) ...
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... ST6208C/ST6209C/ST6210C/ST6220C I/O PORT PIN CHARACTERISTICS (Cont’d) 10.8.2 Output Driving Current Subject to general operating conditions for V Symbol Parameter Output low level voltage for a standard I/O pin (see Figure 63 and Figure Output low level voltage for a high sink I/O pin (see Figure 64 and Figure Output high level voltage for an I/O pin ...
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... Ta=25°C 300 250 200 150 3 4 VDD [V] Figure 67. Typical Vol [V] at Iio=8mA 0.55 0.5 0.45 0.4 0.35 0.3 0.25 0 VDD [V] ST6208C/ST6209C/ST6210C/ST6220C = 5V 5 Ta=-40°C Ta=25° Iio [mA] (standard I/Os) Ta=95°C Vol [mV] at Iio=5mA 700 Ta=125°C 600 500 400 300 5 6 (high-sink I/Os) Vol [V] at Iio=20mA Ta=-40°C Ta=95°C 1 ...
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... ST6208C/ST6209C/ST6210C/ST6220C I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 68. Typical Voh [V] at Iio=-2mA VDD [V] 84/104 1 Voh [V] at Iio=-5mA Ta=-40°C Ta=95°C 3 Ta=25°C Ta=125° Ta=-40°C Ta=95°C Ta=25°C Ta=125° VDD [V] ...
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... The output of the external reset circuit must have an open-drain output to drive the ST6 reset pad. Otherwise the device can be damaged when the ST6 generates an internal reset (LVD or watchdog). Figure 69. Typical Ron [Kohm] 1000 900 800 700 600 500 400 300 200 100 ST6208C/ST6209C/ST6210C/ST6220C , f , and T DD OSC A Conditions = ...
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... ST6208C/ST6209C/ST6210C/ST6220C CONTROL PIN CHARACTERISTICS (Cont’d) Figure 70. Typical Application with RESET pin 0.1μF 4.7kΩ EXTERNAL RESET 7) CIRCUIT 0.1μF 10.9.2 NMI Pin Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis ...
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... Watchdog Timer Symbol Parameter t Watchdog time-out duration w(WDG) 10.10.2 8-Bit Timer Symbol Parameter f Timer external clock frequency EXT t Pulse width at TIMER pin w ST6208C/ST6209C/ST6210C/ST6220C , Refer to I/O port characteristics for more details on DD the input/output alternate function characteristics (TIMER). Conditions Min 3,072 f =4MHz 0.768 CPU f =8MHz ...
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... ST6208C/ST6209C/ST6210C/ST6220C 10.11 8-BIT ADC CHARACTERISTICS Subject to general operating conditions for V Symbol Parameter f Clock frequency OSC V Conversion range voltage AIN R External input resistor AIN t Total convertion time ADC 4) t Stabilization time STAB Analog input current during conver sion AC Analog input capacitance IN Notes: 1 ...
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... DDA 1LSB = ---------------------------------------- - IDEAL 256 253 LSB SSA Note: ADC not present on some devices. See device summary on page 1. ST6208C/ST6209C/ST6210C/ST6220C Conditions = =8MHz OSC SSA ( (3) ( IDEAL 6 7 253 254 255 256 ...
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... ST6208C/ST6209C/ST6210C/ST6220C 11 GENERAL INFORMATION 11.1 PACKAGE MECHANICAL DATA Figure 74. 20-Pin Plastic Dual In-Line Package, 300-mil Width Figure 75. 20-Pin Ceramic Side-Brazed Dual In-Line Package 90/104 CDIP20W mm Dim. Min Typ Max Min A 5. 0.38 0.015 A2 2.92 3.30 4.95 0.115 0.130 0.195 b 0.36 0.46 0.56 0.014 0.018 0.022 b2 1 ...
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... PACKAGE MECHANICAL DATA (Cont’d) Figure 76. 20-Pin Plastic Small Outline Package, 300-mil Width Figure 77. 20-Pin Plastic Shrink Small Outline Package ST6208C/ST6209C/ST6210C/ST6220C h x 45× inches Dim. Min Typ Max Min Typ A 2.35 2.65 0.093 c A1 ...
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... ST6208C/ST6209C/ST6210C/ST6220C 11.2 THERMAL CHARACTERISTICS Symbol Package thermal resistance (junction to ambient) DIP20 R thJA SO20 SSOP20 P Power dissipation D T Maximum junction temperature Jmax Notes: 1. The power dissipation is obtained from the formula P and P is the port power dissipation determined by the user. PORT 2. The average chip-junction temperature can be obtained from the formula T ...
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... ECOPACK INFORMATION In order to meet environmental requirements, ST offers these devices in different grades of ECO- ® PACK packages, depending on their level of en- vironmental compliance. ECOPACK tions, grade definitions and product status are available at: www.st.com. ECOPACK trademark. ST6208C/ST6209C/ST6210C/ST6220C ® specifica- ® 93/104 1 ...
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... ST6208C/ST6209C/ST6210C/ST6220C 11.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL Table 23. Suggested List of DIP20 Socket Types Package / Probe DIP20 TEXTOOL Table 24. Suggested List of SO20 Socket Types Package / Probe ENPLAS SO20 YAMAICHI Adapter from SO20 to DIP20 footprint EMU PROBE (delivered with emulator) Programming Logical Systems Adapter Table 25. Suggested List of SSOP20 Socket Types ...
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... ORDERING INFORMATION The following section deals with the procedure for transfer of customer codes to STMicroelectronics Figure 78. ST6 Factory Coded Device Types ST62T20CB6/CCC ST6208C/ST6209C/ST6210C/ST6220C and also details the ST6 factory coded device type. ROM code Temperature code: 1: Standard 0 to +70 °C 3: Automotive -40 to +125 °C 6: Industrial -40 to +85 ° ...
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... ST6208C/ST6209C/ST6210C/ST6220C 11.6 TRANSFER OF CUSTOMER CODE Customer code is made up of the ROM contents and the list of the selected FASTROM options. The ROM contents are to be sent on diskette electronic means, with the hexadecimal file generated by the development tool. All unused bytes must be set to FFh. ...
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... ST6209C (1 KB ST6220C (4 KB) ...
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... ST6208C/ST6209C/ST6210C/ST6220C 11.6.2 ROM VERSION The ST6208C, 09C, 10C and 20C are mask pro- grammed ROM version of ST62T08C, T09C, T10C and T20C OTP devices. They offer the same functionality as OTP devices, selecting as ROM options the options defined in the programmable option byte of the OTP version. ...
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... SYSTEM GENERAL CORP TRIBAL MICROSYSTEMS XELTEK Note 1: For latest information on third party tools, please visit our Internet site: ➟ http://www.st.com. ST6208C/ST6209C/ST6210C/ST6220C the ST6 from third party manufacturers can be ob- tain from the STMicroelectronics Internet site: ➟ http://www.st.com. ...
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... In-circuit powerful emula- ST6 HDS2 Emulator tion features including trace/ logic analyzer ST6 EPROM No Programmer Board Table 28. Dedicated STMicroelectronics Development Tools Supported Products ST6208C, ST6209C, ST6210C and ST6220C 100/104 1 Programming Capability Yes (DIP packages only) No Yes ST6 Starter Kit ST6 HDS2 Emulator ...
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... SOFTWARE TECHNIQUES FOR IMPROVING ST6 EMC PERFORMANCE PERIPHERAL OPERATIONS AN590 PWM GENERATION WITH ST62 AUTO-RELOAD TIMER AN591 INPUT CAPTURE WITH ST62 AUTO-RELOAD TIMER AN592 PLL GENERATION USING THE ST62 AUTO-RELOAD TIMER AN593 ST62 IN-CIRCUIT PROGRAMMING AN678 LCD DRIVING WITH ST6240 ST6208C/ST6209C/ST6210C/ST6220C DESCRIPTION 101/104 1 ...
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... ST6208C/ST6209C/ST6210C/ST6220C IDENTIFICATION AN913 PWM GENERATION WITH ST62 16-BIT AUTO-RELOAD TIMER AN914 USING ST626X SPI AS UART AN1016 ST6 USING THE ST623XB/ST628XB UART AN1050 ST6 INPUT CAPTURE WITH ST62 16-BIT AUTO-RELOAD TIMER AN1127 USING THE ST62T6XC/5XC SPI IN MASTER MODE GENERAL MCUS - 8/16-BIT MICROCONTROLLERS (MCUS) APPLICATION NOTES ABSTRACTS BY ...
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... Replaced soldering information by ECOPACK Updated disclaimer on last page 15 TO GET MORE INFORMATION To get the latest information on this product please use the STMicroelectronics web server. ➟ http://www.st.com/ ST6208C/ST6209C/ST6210C/ST6220C Main Changes Section 5 and Section 6 76: added text on data retention and program- ® ...
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... ST6208C/ST6209C/ST6210C/ST6220C Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...