ST72321R6 STMicroelectronics, ST72321R6 Datasheet - Page 73

• Manufacturer Part Number: ST72321R6
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72321R6

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt,Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

16-BIT TIMER (Cont’d)
10.4.3.3 Input Capture
In this section, the index, i, may be 1 or 2 because
there are two input capture functions in the 16-bit
timer.
The two 16-bit input capture registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition is detected on the
ICAPi pin (see
ICiR register is a read-only register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
counter: (
Procedure:
To use the input capture function select the follow-
ing in the CR2 register:
– Select the timer clock (CC[1:0]) (see
– Select the edge of the active transition on the
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input or input with
pull-up without interrupt if this configuration is
available).
input capture coming from either the ICAP1 pin
or the ICAP2 pin
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as floating input or input with pull-
up without interrupt if this configuration is availa-
ble).
ICiR
f
CPU
/
Figure
CC[1:0]).
MS Byte
ICiHR
5).
LS Byte
ICiLR
Table
1).
When an input capture occurs:
– ICFi bit is set.
– The ICiR register contains the value of the free
– A timer interrupt is generated if the ICIE bit is set
Clearing the Input Capture interrupt request (that
is, clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
Notes:
1. After reading the ICiHR register, transfer of
2. The ICiR register contains the free running
3. The two input capture functions can be used
4. In One Pulse mode and PWM mode only Input
5. The alternate inputs (ICAP1 and ICAP2) are
6. The TOF bit can be used with interrupt genera-
running counter on the active transition on the
ICAPi pin (see
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
input capture data is inhibited and ICFi will
never be set until the ICiLR register is also
read.
counter value which corresponds to the most
recent input capture.
together even if the timer also uses the two out-
put compare functions.
Capture 2 can be used.
always directly connected to the timer. So any
transitions on these pins activates the input
capture function.
Moreover if one of the ICAPi pins is configured
as an input and the second one as an output,
an interrupt can be generated if the user tog-
gles the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion i is disabled by reading the ICiHR (see note
1).
tion in order to measure events that go beyond
the timer range (FFFFh).
ST72321Rx ST72321ARx ST72321Jx
Figure
6).
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