ST72561K9 STMicroelectronics, ST72561K9 Datasheet - Page 61

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ST72561K9

Manufacturer Part Number
ST72561K9
Description
8-BIT MCU WITH FLASH OR ROM, 10-BIT ADC, 5 TIMERS, SPI, LINSCI(TM), ACTIVE CAN
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72561K9

Hdflash Endurance
100 cycles, data retention 40 years at 85°C
5 Power Saving Modes
Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the CSR register. It indicates when set
that the main oscillator has reached the selected
elapsed time (TB1:0).
0: Timeout not reached
1: Timeout reached
Table 16. Main Clock Controller Register Map and Reset Values
Address
(Hex.)
002Dh
002Eh
SICSR
Reset Value
MCCSR
Reset Value
Register
Label
MCO
7
0
0
AVDIE
CP1
6
0
AVDF
CP0
5
0
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
LVDRF
SMS
4
0
TB1
3
0
0
TB0
2
0
0
OIE
1
0
0
ST72561
WDGRF
OIF
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0
x
0

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