ST7MC2S4 STMicroelectronics, ST7MC2S4 Datasheet - Page 65

• Manufacturer Part Number: ST7MC2S4
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
• Manufacturer: STMicroelectronics

WINDOW WATCHDOG (Cont’d)
10.1.9 Interrupts
None.
10.1.10 Register Description
CONTROL REGISTER (WDGCR)
Read/Write
Reset Value: 0111 1111 (7Fh)
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bits 6:0 = T[6:0] 7-bit counter (MSB to LSB).
These bits contain the value of the watchdog
counter. It is decremented every 16384 f
cles (approx.). A reset is produced when it rolls
over from 40h to 3Fh (T6 becomes cleared).
WDGA
7
T6
T5
T4
T3
T2
T1
OSC2
T0
0
cy-
WINDOW REGISTER (WDGWR)
Read/Write
Reset Value: 0111 1111 (7Fh)
Bit 7 = Reserved
Bits 6:0 = W[6:0] 7-bit window value
These bits contain the window value to be com-
pared to the downcounter.
7
-
W6
W5
W4
ST7MC1xx/ST7MC2xx
W3
W2
W1
65/309
W0
0
1