ST72321M9 STMicroelectronics, ST72321M9 Datasheet
ST72321M9
Specifications of ST72321M9
Related parts for ST72321M9
ST72321M9 Summary of contents
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... Development tools ■ – Full hardware/software development package – In-circuit testing capability ST72321M9 60 Kbytes 2048 bytes (256 bytes) 3 5.5 V -40 °C to +85 °C LQFP80 14x14 Doc ID 12706 Rev 2 ST72321M6 ST72321M9 2 C interface LQFP80 ST72321M6 32 Kbytes 1024 (256 bytes) 1/175 1 ...
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INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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TIMER PWM MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... CORE ALU CONTROL LVD AVD OSC MCC/RTC/BEEP PORT F TIMER A BEEP PORT E SCI PORT D 10-BIT ADC ST72321M6 ST72321M9 PROGRAM MEMORY ( Kbytes) RAM (1024-2048 Bytes) WATCHDOG I2C PA7:0 (8-bits) PORT A PORT B PB7:0 (8-bits) PWM ART PORT C ...
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... ST72321M6 ST72321M9 2 PIN DESCRIPTION Figure 2. 80-Pin LQFP 14x14 Package Pinout (HS) PE4 1 (HS) PE5 2 (HS) PE6 3 (HS) PE7 4 PWM3 / PB0 5 PWM2 / PB1 6 PWM1 / PB2 7 PWM0 / PB3 8 PG0 9 PG1 10 PG2 11 PG3 12 ARTCLK / (HS) PB4 13 ARTIC1 / PB5 14 ARTIC2 / PB6 15 PB7 16 AIN0 / PD0 17 AIN1 / PD1 18 AIN2 / PD2 ...
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... ST72321M6 ST72321M9 1) , ana = analog Main function Alternate function (after reset Port Port Port Port Port B0 PWM Output Port B1 PWM Output ...
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... ST72321M6 ST72321M9 Pin n° Pin Name 26 PD7/AIN7 AREF SSA DD_3 SS_3 31 PG4 32 PG5 33 PF0/MCO/AIN8 34 PF1 (HS)/BEEP 35 PF2 (HS) 36 PF3/OCMP2_A/AIN9 37 PF4/OCMP1_A/AIN10 38 PF5/ICAP2_A/AIN11 39 PF6 (HS)/ICAP1_A 40 PF7 (HS)/EXTCLK_A DD_0 SS_0 43 PC0/OCMP2_B/AIN12 44 PC1/OCMP1_B/AIN13 45 PC2 (HS)/ICAP2_B 46 PC3 (HS)/ICAP1_B 47 PC4/MISO/ICCDATA 48 PC5/MOSI/AIN14 ...
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... and V pins to the supply voltage and all V DD REF ST72321M6 ST72321M9 Main function Alternate function (after reset) SPI Serial Clock X X Port C6 Caution: Negative current injection not allowed on this pin SPI Slave X X Port C7 ...
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... ST72321M6 ST72321M9 pins to ground. 3. OSC1 and OSC2 pins connect a crystal/ceramic resonator external source to the on-chip oscil- lator the chip, each I/O port may have pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid add- ed current consumption the open drain output column, “ ...
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... Related Documentation AN 985: Executing Code in ST7 RAM 0080h Short Addressing RAM (zero page) 00FFh 0100h 256 Bytes Stack 01FFh 0200h 16-bit Addressing RAM or 047Fh or 067Fh or 087Fh ST72321M6 ST72321M9 1000h 60 Kbytes 8000h 32 Kbytes FFFFh 13/175 ...
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... ST72321M6 ST72321M9 Table 3. Hardware Register Map Register Address Block 0000h PADR 2) 0001h Port A PADDR 0002h PAOR 0003h PBDR 2) 0004h Port B PBDDR 0005h PBOR 0006h PCDR 0007h Port C PCDDR 0008h PCOR 0009h PDDR 2) 000Ah Port D PDDDR 000Bh PDOR 000Ch PEDR 2) 000Dh Port E ...
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... Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register ST72321M6 ST72321M9 Reset Remarks Status FFh R/W FFh ...
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... ST72321M6 ST72321M9 Register Address Block 0050h SCISR 0051h SCIDR 0052h SCIBRR 0053h SCICR1 SCI 0054h SCICR2 0055h SCIERPR 0056h 0057h SCIETPR 0058h to 006Fh 0070h ADCCSR 0071h ADC ADCDRH 0072h ADCDRL 0073h PWMDCR3 0074h PWMDCR2 0075h PWMDCR1 0076h PWMDCR0 0077h PWMCR 0078h ...
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... Note: The LVD is not supported if read-out protec- tion is enabled. 10K 16K 24K 32K 2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 4 Kbytes 4 Kbytes ST72321M6 ST72321M9 Table 4). Each of these sectors can 4). They are mapped in the upper part Available Sectors 4 Sector 0 8 Sectors 0,1 > 8 Sectors 0,1, 2 48K 60K ...
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... ST72321M6 ST72321M9 FLASH PROGRAM MEMORY (Cont’d) 4.4 ICC Interface ICC needs a minimum of 4 and pins to be connected to the programming tool (see These pins are: – RESET: device reset – device power supply ground SS Figure 5. Typical ICC Interface PROGRAMMING TOOL (See Note 3) ...
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... ST72321M6 ST72321M9 FLASH PROGRAM MEMORY (Cont’d) 4.5 ICP (In-Circuit Programming) To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool. Depending on the ICP code downloaded in RAM, Flash memory programming can be fully custom- ized (number of bytes to program, program loca- tions, or selection serial communication interface for downloading) ...
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... ST72321M6 ST72321M9 5 CENTRAL PROCESSING UNIT 5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES Enable executing 63 basic instructions ■ Fast 8-bit by 8-bit multiply ■ 17 main addressing modes (with indirect ■ addressing mode) Two 8-bit index registers ■ ...
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... ST72321M6 ST72321M9 CENTRAL PROCESSING UNIT (Cont’d) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP in- structions ...
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... ST72321M6 ST72321M9 CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 FFh SP7 SP6 SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is al- ways pointing to the next free location in the stack then decremented after data has been pushed ...
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... ST72321M6 ST72321M9 6 SUPPLY, RESET AND CLOCK MANAGEMENT The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. An overview is shown in Figure 10. For more details, refer to dedicated parametric section. ...
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... ST72321M6 ST72321M9 6.2 MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by three different source types coming from the multi- oscillator block: an external source ■ 4 crystal or ceramic resonator oscillators ■ an internal high frequency RC oscillator ■ Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte ...
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... ST72321M6 ST72321M9 6.3 RESET SEQUENCE MANAGER (RSM) 6.3.1 Introduction The reset sequence manager includes three RE- SET sources as shown in Figure External RESET source pulse ■ Internal LVD RESET (Low Voltage Detection) ■ Internal WATCHDOG RESET ■ These sources act on the RESET pin and it is al- ways kept low during the delay phase ...
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... ST72321M6 ST72321M9 RESET SEQUENCE MANAGER (Cont’d) The RESET pin is an asynchronous signal which plays a major role in EMS performance noisy environment recommended to follow the guidelines mentioned in the electrical characteris- tics section. If the external RESET pulse is shorter than t (see short ext. Reset in w(RSTL)out signal on the RESET pin may be stretched ...
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... ST72321M6 ST72321M9 6.4 SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains the Low Voltage Detector (LVD), and Auxiliary Voltage Detector (AVD) functions managed by the SICSR register. 6.4.1 Low Voltage Detector (LVD) The Low Voltage Detector function (LVD) gener- ates a static reset when the V below a V reference value ...
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... ST72321M6 ST72321M9 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between reference value and the V IT+(AVD) ply or the external EVD pin voltage level (V The V reference value for falling voltage is lower ...
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... ST72321M6 ST72321M9 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.2.2 Monitoring a Voltage on the EVD pin This mode is selected by setting the AVDS bit in the SICSR register. The AVD circuitry can generate an interrupt when the AVDIE bit of the SICSR register is set. This in- terrupt is generated on the rising and falling edges Figure 16 ...
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... ST72321M6 ST72321M9 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.3 Low Power Modes Mode Description No effect on SI. AVD interrupts cause the WAIT device to exit from Wait mode. HALT The CRSR register is frozen. 6.4.3.1 Interrupts The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is ...
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... ST72321M6 ST72321M9 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write Reset Value: 000x 000x (00h) 7 AVD AVD AVD LVD Bit 7 = AVDS Voltage Detection selection This bit is set and cleared by software. Voltage De- tection is available only if the LVD is enabled by option byte ...
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... ST72321M6 ST72321M9 7 INTERRUPTS 7.1 INTRODUCTION The ST7 enhanced interrupt management pro- vides the following features: Hardware interrupts ■ Software interrupt (TRAP) ■ Nested or concurrent interrupt management ■ with flexible interrupt management: – software programmable nesting levels – interrupt vectors fixed by hardware – ...
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... ST72321M6 ST72321M9 INTERRUPTS (Cont’d) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is deter- mined by the following two-step process: – the highest software priority interrupt is serviced, – if several interrupts have the same software pri- ority then the interrupt with the highest hardware priority is serviced first ...
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... ST72321M6 ST72321M9 INTERRUPTS (Cont’d) 7.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see column “Exit from HALT” in “Interrupt Mapping” table). When ...
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... ST72321M6 ST72321M9 INTERRUPTS (Cont’d) 7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read/Write Reset Value: 111x 1010 (xAh Bit I1, I0 Software Interrupt Priority These two bits indicate the current interrupt soft- ware priority. Interrupt Software Priority Level ...
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... ST72321M6 ST72321M9 INTERRUPTS (Cont’d) Table 7. Dedicated Interrupt Instruction Set Instruction New Description HALT Entering Halt mode IRET Interrupt routine return JRM Jump if I1:0=11 (level 3) JRNM Jump if I1:0<>11 POP CC Pop CC from the Stack RIM Enable interrupt (level 0 set) SIM Disable interrupt (level 3 set) ...
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... ST72321M6 ST72321M9 INTERRUPTS (Cont’d) Table 8. Interrupt Mapping Source N° Block RESET Reset TRAP Software interrupt 0 TLI External top level interrupt 1 MCC/RTC Main clock controller time base interrupt 2 ei0 External interrupt port A3..0 3 ei1 External interrupt port F2..0 4 ei2 External interrupt port B3..0 5 ei3 External interrupt port B7 ...
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... ST72321M6 ST72321M9 INTERRUPTS (Cont’d) Figure 21. External Interrupt Control bits PORT A [3:0] INTERRUPTS PAOR.3 PADDR.3 PA3 IPA BIT PORT F [2:0] INTERRUPTS PFOR.2 PFDDR.2 PF2 PORT B [3:0] INTERRUPTS PBOR.3 PBDDR.3 PB3 IPB BIT PORT B [7:4] INTERRUPTS PBOR.7 PBDDR.7 PB7 38/175 EICR IS20 IS21 SENSITIVITY PA3 PA2 ...
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... ST72321M6 ST72321M9 7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read/Write Reset Value: 0000 0000 (00h) 7 IS11 IS10 IPB IS21 IS20 Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts: - ei2 (port B3..0) External Interrupt Sensitivity ...
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... ST72321M6 ST72321M9 INTERRUPTS (Cont’d) Table 9. Nested Interrupts Register Map and Reset Values Address Register 7 (Hex.) Label 0024h I1_3 ISPR0 1 Reset Value 0025h I1_7 ISPR1 1 Reset Value 0026h ISPR2 I1_11 1 Reset Value 0027h ISPR3 Reset Value 1 EICR IS11 0028h Reset Value ...
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... ST72321M6 ST72321M9 8 POWER SAVING MODES 8.1 INTRODUCTION To give a large measure of flexibility to the applica- tion in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 22): Slow, Wait (Slow wait), Active-halt and Halt. After a RESET the normal operating mode is se- lected by default (RUN mode) ...
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... ST72321M6 ST72321M9 POWER SAVING MODES (Cont’d) 8.3 WAIT MODE WAIT mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. During WAIT mode, the I[1:0] bits of the CC register are forced to ‘10’, to enable all interrupts ...
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... ST72321M6 ST72321M9 POWER SAVING MODES (Cont’d) 8.4 ACTIVE-HALT AND HALT MODES Active-halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active-halt or Halt mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR register) ...
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... ST72321M6 ST72321M9 POWER SAVING MODES (Cont’d) 8.4.2 HALT MODE The Halt mode is the lowest power consumption mode of the MCU entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see section 9.2 on page 53 tails on the MCCSR register) ...
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... ST72321M6 ST72321M9 POWER SAVING MODES (Cont’d) 8.4.2.1 Halt Mode Recommendations – Make sure that an external event is available to wake up the microcontroller from Halt mode. – When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction ...
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... ST72321M6 ST72321M9 I/O PORTS (Cont’d) 8.4.3 I/O Port Implementation The I/O port register configurations are summa- rised as follows. Standard Ports PA5:4, PC7:0, PD7:0, PE7:34, PE1:0, PF7:3, PG7:0, PH7:0 MODE floating input pull-up input open drain output push-pull output Interrupt Ports PA2:0, PB6:5, PB4, PB2:0, PF1:0 (with pull-up) ...
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... ST72321M6 ST72321M9 I/O PORTS (Cont’d) Table 11. I/O Port Register Map and Reset Values Address Register 7 (Hex.) Label Reset Value 0 of all I/O port registers 0000h PADR 0001h PADDR MSB 0002h PAOR 0003h PBDR 0004h PBDDR MSB 0005h PBOR 0006h PCDR 0007h PCDDR MSB ...
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... ST72321M6 ST72321M9 9 ON-CHIP PERIPHERALS 9.1 WATCHDOG TIMER (WDG) 9.1.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. The Watchdog cir- ...
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... ST72321M6 ST72321M9 WATCHDOG TIMER (Cont’d) 9.1.4 How to Program the Watchdog Timeout Figure 30 shows the linear relationship between the 6-bit value to be loaded in the Watchdog Coun- ter (CNT) and the resulting timeout duration in mil- liseconds. This can be used for a quick calculation without taking the timing variations into account. If Figure 30 ...
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... ST72321M6 ST72321M9 WATCHDOG TIMER (Cont’d) Figure 31. Exact Timeout Duration (t WHERE (LSB + 128 min0 OSC2 t = 16384 x t max0 OSC2 t = 125 MHz OSC2 OSC2 CNT = Value of T[5:0] bits in the WDGCR register (6 bits) MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits ...
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... ST72321M6 ST72321M9 WATCHDOG TIMER (Cont’d) 9.1.5 Low Power Modes Mode Description SLOW No effect on Watchdog. WAIT No effect on Watchdog. OIE bit in WDGHALT bit MCCSR in Option register Byte 0 HALT 0 1 9.1.6 Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the WDGCR is not used ...
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... ST72321M6 ST72321M9 Table 12. Watchdog Timer Register Map and Reset Values Address Register 7 (Hex.) Label WDGCR WDGA 002Ah Reset Value 0 52/175 ...
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... ST72321M6 ST72321M9 9.2 MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK AND BEEPER (MCC/RTC) The Main Clock Controller consists of three differ- ent functions: a programmable CPU clock prescaler ■ a clock-out signal to supply external devices ■ a real-time clock timer with interrupt capability ■ Each function can be used independently and si- multaneously ...
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... ST72321M6 ST72321M9 MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK (Cont’d) 9.2.5 Low Power Modes Mode Description No effect on MCC/RTC peripheral. Wait MCC/RTC interrupt cause the device to exit from Wait mode. No effect on MCC/RTC counter (OIE bit is Active- set), the registers are frozen. halt MCC/RTC interrupt cause the device to exit from Active-halt mode ...
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... ST72321M6 ST72321M9 MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK (Cont’d) Bit 0 = OIF Oscillator interrupt flag This bit is set by hardware and cleared by software reading the MCCSR register. It indicates when set that the main oscillator has reached the selected elapsed time (TB1:0). 0: Timeout not reached ...
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... ST72321M6 ST72321M9 9.3 PWM AUTO-RELOAD TIMER (ART) 9.3.1 Introduction The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit auto reload counter with compare/capture capabilities and of a 7-bit prescaler clock source. These resources allow five possible operating modes: – Generation independent PWM signals – ...
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... ST72321M6 ST72321M9 ON-CHIP PERIPHERALS (Cont’d) 9.3.2 Functional Description Counter The free running 8-bit counter is fed by the output of the prescaler, and is incremented on every ris- ing edge of the clock signal possible to read or write the contents of the counter on the fly by reading or writing the Counter Access register (ARTCAR) ...
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... ST72321M6 ST72321M9 ON-CHIP PERIPHERALS (Cont’d) Independent PWM signal generation This mode allows up to four Pulse Width Modulat- ed signals to be generated on the PWMx output pins with minimum core processing overhead. This function is stopped during HALT mode. Each PWMx output signal can be selected inde- pendently using the corresponding OEx bit in the PWM Control register (PWMCR) ...
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... ST72321M6 ST72321M9 ON-CHIP PERIPHERALS (Cont’d) Output compare and Time base interrupt On overflow, the OVF flag of the ARTCSR register is set and an overflow interrupt request is generat the overflow interrupt enable bit, OIE, in the ARTCSR register, is set. The OVF flag must be re- set by the user software ...
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... ST72321M6 ST72321M9 ON-CHIP PERIPHERALS (Cont’d) Input capture function This mode allows the measurement of external signal pulse widths through ARTICRx registers. Each input capture can generate an interrupt inde- pendently on a selected input signal transition. This event is flagged by a set of the corresponding CFx bits of the Input Capture Control/Status regis- ter (ARTICCSR) ...
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... ST72321M6 ST72321M9 ON-CHIP PERIPHERALS (Cont’d) 9.3.3 Register Description CONTROL / STATUS REGISTER (ARTCSR) Read/Write Reset Value: 0000 0000 (00h) 7 EXCL CC2 CC1 CC0 TCE Bit 7 = EXCL External Clock This bit is set and cleared by software. It selects the input clock for the 7-bit prescaler. ...
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... ST72321M6 ST72321M9 ON-CHIP PERIPHERALS (Cont’d) PWM CONTROL REGISTER (PWMCR) Read/Write Reset Value: 0000 0000 (00h) 7 OE3 OE2 OE1 OE0 OP3 Bit 7:4 = OE[3:0] PWM Output Enable These bits are set and cleared by software. They enable or disable the PWM output channels inde- pendently acting on the corresponding I/O pin. ...
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... ST72321M6 ST72321M9 ON-CHIP PERIPHERALS (Cont’d) INPUT CAPTURE CONTROL / STATUS REGISTER (ARTICCSR) Read/Write Reset Value: 0000 0000 (00h CS2 CS1 CIE2 Bit 7:6 = Reserved, always read as 0. Bit 5:4 = CS[2:1] Capture Sensitivity These bits are set and cleared by software. They determine the trigger event polarity on the corre- sponding input capture channel ...
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... ST72321M6 ST72321M9 PWM AUTO-RELOAD TIMER (Cont’d) Table 14. PWM Auto-Reload Timer Register Map and Reset Values Address Register 7 Label (Hex.) PWMDCR3 DC7 0073h 0 Reset Value PWMDCR2 DC7 0074h 0 Reset Value PWMDCR1 DC7 0075h 0 Reset Value PWMDCR0 DC7 0076h 0 Reset Value PWMCR ...
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... ST72321M6 ST72321M9 9.4 16-BIT TIMER 9.4.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input sig- nals (input capture) or generation two out- put waveforms (output compare and PWM). ...
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... ST72321M6 ST72321M9 16-BIT TIMER (Cont’d) Figure 39. Timer Block Diagram f CPU 8 high EXEDG 1/2 COUNTER 1/4 REGISTER 1/8 ALTERNATE EXTCLK pin COUNTER REGISTER CC[1:0] OVERFLOW DETECT CIRCUIT ICF1 OCF1 TOF ICF2 (Control/Status Register) ICIE OCIE TOIE FOLV2 (See note) TIMER INTERRUPT 66/175 ST7 INTERNAL BUS ...
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... ST72321M6 ST72321M9 16-BIT TIMER (Cont’d) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MS Byte At t0 Other instructions Returns the buffered Read At t0 +Δt LS Byte value Byte Sequence completed The user must read the MS Byte first, then the LS Byte value is buffered automatically ...
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... ST72321M6 ST72321M9 16-BIT TIMER (Cont’d) Figure 40. Counter Timing Diagram, Internal Clock Divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 41. Counter Timing Diagram, Internal Clock Divided by 4 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 42 ...
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... ST72321M6 ST72321M9 16-BIT TIMER (Cont’d) 9.4.3.3 Input Capture In this section, the index, i, may because there are two input capture functions in the 16-bit timer. The two 16-bit input capture registers (IC1R and IC2R) are used to latch the value of the free run- ...
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... ST72321M6 ST72321M9 16-BIT TIMER (Cont’d) Figure 43. Input Capture Block Diagram ICAP1 pin EDGE DETECT CIRCUIT2 ICAP2 pin IC2R Register 16-BIT 16-BIT FREE RUNNING COUNTER Figure 44. Input Capture Timing Diagram TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER Note: The rising edge is the active edge. ...
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... ST72321M6 ST72321M9 16-BIT TIMER (Cont’d) 9.4.3.4 Output Compare In this section, the index, i, may because there are two output compare functions in the 16- bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Com- ...
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... ST72321M6 ST72321M9 16-BIT TIMER (Cont’d) Notes: 1. After a processor write cycle to the OCiHR reg- ister, the output compare function is inhibited until the OCiLR register is also written the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set ...
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... ST72321M6 ST72321M9 16-BIT TIMER (Cont’d) Figure 46. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi = 1) Figure 47. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) ...
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... ST72321M6 ST72321M9 16-BIT TIMER (Cont’d) 9.4.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the Input Capture1 function and the Output Compare1 function. ...
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... ST72321M6 ST72321M9 16-BIT TIMER (Cont’d) Figure 48. One Pulse Mode Timing Example IC1R 01F8 COUNTER ICAP1 OCMP1 Note: IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1 Figure 49. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions COUNTER 34E2 OCMP1 compare2 Note: OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1 Note: On timers with only one Output Compare register, a fixed frequency PWM signal can be generated using the output compare and the counter overflow to define the pulse length ...
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... ST72321M6 ST72321M9 16-BIT TIMER (Cont’d) 9.4.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R regis- ter, and so this functionality can not be used when PWM mode is activated ...
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... ST72321M6 ST72321M9 16-BIT TIMER (Cont’d) 9.4.4 Low Power Modes Mode No effect on 16-bit Timer. WAIT Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken interrupt with “ ...
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... ST72321M6 ST72321M9 16-BIT TIMER (Cont’d) 9.4.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. CONTROL REGISTER 1 (CR1) ...
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... ST72321M6 ST72321M9 16-BIT TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Com- pare mode, both OLV1 and OLV2 in PWM and one-pulse mode) ...
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... ST72321M6 ST72321M9 16-BIT TIMER (Cont’d) CONTROL/STATUS REGISTER (CSR) Read/Write (bits 7:3 read only) Reset Value: xxxx x0xx (xxh) 7 ICF1 OCF1 TOF ICF2 OCF2 TIMD Bit 7 = ICF1 Input Capture Flag input capture (reset value input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode ...
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... ST72321M6 ST72321M9 16-BIT TIMER (Cont’d) INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). 7 MSB INPUT CAPTURE 1 LOW REGISTER (IC1LR) ...
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... ST72321M6 ST72321M9 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB OUTPUT COMPARE 2 (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register ...
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... ST72321M6 ST72321M9 16-BIT TIMER (Cont’d) Table 16. 16-Bit Timer Register Map and Reset Values Address Register 7 (Hex.) Label Timer A: 32 CR1 ICIE Timer B: 42 Reset Value Timer A: 31 CR2 OC1E Timer B: 41 Reset Value Timer A: 33 CSR ICF1 Timer B: 43 Reset Value ...
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... ST72321M6 ST72321M9 9.5 SERIAL PERIPHERAL INTERFACE (SPI) 9.5.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI interface can not be a master in a multi-master system ...
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... ST72321M6 ST72321M9 SERIAL PERIPHERAL INTERFACE (Cont’d) – SS: Slave select: This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves indi- vidually and to avoid contention on the data lines. Slave SS inputs can be driven by stand- ard I/O ports on the master MCU. ...
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... ST72321M6 ST72321M9 SERIAL PERIPHERAL INTERFACE (Cont’d) 9.5.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM bit in the SPICSR regis- ter (see Figure ...
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... ST72321M6 ST72321M9 SERIAL PERIPHERAL INTERFACE (Cont’d) 9.5.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: The idle state of SCK must correspond to ...
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... ST72321M6 ST72321M9 SERIAL PERIPHERAL INTERFACE (Cont’d) 9.5.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 54). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0) ...
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... ST72321M6 ST72321M9 SERIAL PERIPHERAL INTERFACE (Cont’d) 9.5.5 Error Flags 9.5.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: – The MODF bit is set and an SPI interrupt re- quest is generated if the SPIE bit is set. ...
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... ST72321M6 ST72321M9 SERIAL PERIPHERAL INTERFACE (Cont’d) 9.5.5.4 Single Master Systems A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see Figure 56). The master device selects the individual slave de- vices by using four pins of a parallel port to control the four SS pins of the slave devices ...
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... ST72321M6 ST72321M9 SERIAL PERIPHERAL INTERFACE (Cont’d) 9.5.6 Low Power Modes Mode Description No effect on SPI. Wait SPI interrupt events cause the device to exit from Wait mode. SPI registers are frozen. In Halt mode, the SPI is inactive. SPI opera- tion resumes when the MCU is woken interrupt with “ ...
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... ST72321M6 ST72321M9 SERIAL PERIPHERAL INTERFACE (Cont’d) 9.5.8 Register Description CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever ...
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... ST72321M6 ST72321M9 SERIAL PERIPHERAL INTERFACE (Cont’d) CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) 7 SPIF WCOL OVR MODF Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only). This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the SPICR register ...
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... ST72321M6 ST72321M9 SERIAL PERIPHERAL INTERFACE (Cont’d) Table 18. SPI Register Map and Reset Values Address Register 7 (Hex.) Label SPIDR MSB 0021h Reset Value SPICR SPIE 0022h Reset Value SPICSR SPIF 0023h Reset Value 94/175 SPE SPR2 MSTR WCOL ...
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... ST72321M6 ST72321M9 9.6 SERIAL COMMUNICATIONS INTERFACE (SCI) 9.6.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI of- fers a very wide range of baud rates using two baud rate generator systems. ...
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... ST72321M6 ST72321M9 SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 57. SCI Block Diagram Write Transmit Data Register (TDR) TDO Transmit Shift Register RDI TRANSMIT CONTROL CR2 TIE TCIE RIE SCI INTERRUPT CONTROL TRANSMITTER CLOCK f CPU 96/175 Read Received Data Register (RDR SCID ...
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... ST72321M6 ST72321M9 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.6.4 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 57 It contains six dedicated reg- isters: – Two control registers (SCICR1 & SCICR2) – A status register (SCISR) – A baud rate register (SCIBRR) – An extended prescaler receiver register (SCIER- PR) – ...
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... ST72321M6 ST72321M9 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.6.4.2 Transmitter The transmitter can send data words of either bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the SCICR1 register ...
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... ST72321M6 ST72321M9 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.6.4.3 Receiver The SCI can receive data words of either bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register. Character reception During a SCI reception, data shifts in least signifi- cant bit first through the RDI pin ...
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... ST72321M6 ST72321M9 SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 59. SCI Baud Rate and Extended Prescaler Block Diagram EXTENDED PRESCALER TRANSMITTER RATE CONTROL EXTENDED TRANSMITTER PRESCALER REGISTER EXTENDED RECEIVER PRESCALER REGISTER EXTENDED PRESCALER RECEIVER RATE CONTROL f CPU /PR /16 SCP1 CONVENTIONAL BAUD RATE GENERATOR ...
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... ST72321M6 ST72321M9 SERIAL COMMUNICATIONS INTERFACE (Cont’d) Framing Error A framing error is detected when: – The stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. – A break is received. When the framing error is detected: – the FE bit is set by hardware – ...
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... ST72321M6 ST72321M9 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.6.4.7 Parity Control Parity control (generation of parity bit in transmis- sion and parity checking in reception) can be ena- bled by setting the PCE bit in the SCICR1 register. Depending on the frame length defined by the M bit, the possible SCI frame formats are as listed in Table 19 ...
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... ST72321M6 ST72321M9 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.6.4.9 Clock Deviation Causes The causes which contribute to the total deviation are: – Deviation due to transmitter error (Local TRA oscillator error of the transmitter or the trans- mitter is transmitting at a different baud rate). – Error due to the baud rate quantiza- QUANT tion of the receiver ...
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... ST72321M6 ST72321M9 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.6.5 Low Power Modes Mode Description No effect on SCI. WAIT SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. HALT In Halt mode, the SCI stops transmitting/re- ceiving until Halt mode is exited. 104/175 9 ...
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... ST72321M6 ST72321M9 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.6.7 Register Description STATUS REGISTER (SCISR) Read Only Reset Value: 1100 0000 (C0h) 7 TDRE TC RDRF IDLE OR Bit 7 = TDRE Transmit data register empty. This bit is set by hardware when the content of the TDR register has been transferred into the shift register ...
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... ST72321M6 ST72321M9 SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (SCICR1) Read/Write Reset Value: x000 0000 (x0h SCID M WAKE Bit Receive data bit 8. This bit is used to store the 9th bit of the received word when Bit Transmit data bit 8. ...
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... ST72321M6 ST72321M9 SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 2 (SCICR2) Read/Write Reset Value: 0000 0000 (00h) 7 TIE TCIE RIE ILIE TE Bit 7 = TIE Transmitter interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever TDRE=1 in the SCISR register ...
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... ST72321M6 ST72321M9 SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (SCIDR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data char- acter, depending on whether it is read from or writ- ten to. 7 DR7 DR6 DR5 DR4 DR3 The Data register performs a double function (read ...
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... ST72321M6 ST72321M9 SERIAL COMMUNICATIONS INTERFACE (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (SCIERPR) Read/Write Reset Value: 0000 0000 (00h) Allows setting of the Extended Prescaler rate divi- sion factor for the receive circuit. 7 ERPR ERPR ERPR ERPR ERPR Bits 7:0 = ERPR[7:0] 8-bit Extended Receive Prescaler Register ...
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... ST72321M6 ST72321M9 SERIAL COMMUNICATION INTERFACE (Cont’d) Table 21. SCI Register Map and Reset Values Address Register 7 (Hex.) Label SCISR TDRE 0050h Reset Value 1 SCIDR MSB 0051h Reset Value x SCIBRR SCP1 0052h Reset Value 0 SCICR1 R8 0053h Reset Value x SCICR2 TIE 0054h Reset Value ...
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... ST72321M6 ST72321M9 2 9 BUS INTERFACE (I2C) 9.7.1 Introduction 2 The I C Bus Interface serves as an interface be- tween the microcontroller and the serial I provides both multimaster and slave functions, 2 and controls all I C bus-specific sequencing, pro- tocol, arbitration and timing. It supports fast I mode (400 kHz). ...
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... ST72321M6 ST72321M9 BUS INTERFACE (Cont’d) Acknowledge may be enabled and disabled by software. 2 The I C interface address and/or general call ad- dress can be selected by software. 2 The speed of the I C interface may be selected between Standard (up to 100 kHz) and Fast I (up to 400 kHz). ...
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... ST72321M6 ST72321M9 BUS INTERFACE (Cont’d) 9.7.4 Functional Description Refer to the CR, SR1 and SR2 registers in 9.7.7. for the bit definitions default the I C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence. First the interface frequency must be configured using the FRi bits in the OAR2 register ...
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... ST72321M6 ST72321M9 INTERFACE (Cont’d) How to release the SDA / SCL lines Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released after the transfer of the current byte. SMBus Compatibility 2 ST7 compatible with SMBus V1.1 protocol. It supports all SMBus adressing modes, SMBus bus protocols and CRC-8 packet error checking ...
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... ST72321M6 ST72321M9 BUS INTERFACE (Cont’d) Master Transmitter Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the inter- nal shift register. The master waits for a read of the SR1 register fol- ...
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... ST72321M6 ST72321M9 BUS INTERFACE (Cont’d) Figure 63. Transfer Sequencing 7-bit Slave receiver: S Address A Data1 EV1 7-bit Slave transmitter: S Address A Data1 EV1 EV3 7-bit Master receiver: S Address A EV5 EV6 7-bit Master transmitter: S Address A EV5 EV6 EV8 10-bit Slave receiver: S Header A Address ...
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... ST72321M6 ST72321M9 BUS INTERFACE (Cont’d) 9.7.5 Low Power Modes Mode 2 No effect interface. Wait interrupts cause the device to exit from Wait mode registers are frozen. 2 Halt In Halt mode, the I C interface is inactive and does not acknowledge data on the bus. The I resumes operation when the MCU is woken interrupt with “ ...
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... ST72321M6 ST72321M9 BUS INTERFACE (Cont’d) 9.7.7 Register Description CONTROL REGISTER (CR) Read / Write Reset Value: 0000 0000 (00h ENGC START ACK Bit 7:6 = Reserved. Forced hardware. Bit Peripheral enable. This bit is set and cleared by software. 0: Peripheral disabled ...
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... ST72321M6 ST72321M9 BUS INTERFACE (Cont’ STATUS REGISTER 1 (SR1) Read Only Reset Value: 0000 0000 (00h) 7 EVF ADD10 TRA BUSY BTF Bit 7 = EVF Event flag. This bit is set by hardware as soon as an event oc- curs cleared by software reading SR2 register ...
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... ST72321M6 ST72321M9 BUS INTERFACE (Cont’d) Bit 1 = M/SL Master/Slave. This bit is set by hardware as soon as the interface is in Master mode (writing START=1 cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO=1 also cleared when the interface is disabled (PE=0). ...
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... ST72321M6 ST72321M9 BUS INTERFACE (Cont’ CLOCK CONTROL REGISTER (CCR) Read / Write Reset Value: 0000 0000 (00h) 7 FM/SM CC6 CC5 CC4 CC3 Bit 7 = FM/SM Fast/Standard I This bit is set and cleared by software not cleared when the interface is disabled (PE=0 Standard I C mode ...
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... ST72321M6 ST72321M9 BUS INTERFACE (Cont’ OWN ADDRESS REGISTER (OAR1) Read / Write Reset Value: 0000 0000 (00h) 7 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 7-bit Addressing Mode Bit 7:1 = ADD[7:1] Interface address. 2 These bits define the I C bus address of the inter- face ...
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... ST72321M6 ST72321M9 I²C BUS INTERFACE (Cont’d) 2 Table 22 Register Map and Reset Values Address Register 7 Label (Hex.) I2CCR 0018h Reset Value 0 I2CSR1 EVF 0019h Reset Value 0 I2CSR2 001Ah Reset Value 0 I2CCCR FM/SM 001Bh Reset Value 0 I2COAR1 ADD7 001Ch Reset Value 0 I2COAR2 ...
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... ST72321M6 ST72321M9 9.8 10-BIT A/D CONVERTER (ADC) 9.8.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 10-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from different sources ...
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... ST72321M6 ST72321M9 10-BIT A/D CONVERTER (ADC) (Cont’d) 9.8.3 Functional Description The conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. If the input voltage ( greater than V AIN (high-level voltage reference) then the conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without overflow indication) ...
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... ST72321M6 ST72321M9 10-BIT A/D CONVERTER (ADC) (Cont’d) 9.8.6 Register Description CONTROL/STATUS REGISTER (ADCCSR) Read/Write (Except bit 7 read only) Reset Value: 0000 0000 (00h) 7 EOC SPEED ADON 0 CH3 Bit 7 = EOC End of Conversion This bit is set by hardware cleared by hard- ware when software reads the ADCDRH register or writes to any bit of the ADCCSR register ...
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... ST72321M6 ST72321M9 10-BIT A/D CONVERTER (Cont’d) Table 23. ADC Register Map and Reset Values Address Register 7 (Hex.) Label ADCCSR EOC 0070h Reset Value 0 ADCDRH D9 0071h Reset Value 0 ADCDRL 0072h Reset Value 0 127/175 SPEED ADON ...
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... ST72321M6 ST72321M9 10 INSTRUCTION SET 10.1 CPU ADDRESSING MODES The CPU features 17 different addressing modes which can be classified in seven main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) Relative jrne loop Bit operation bset The CPU Instruction set is designed to minimize the number of bytes required per instruction Table 24 ...
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... ST72321M6 ST72321M9 INSTRUCTION SET OVERVIEW (Cont’d) 10.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction NOP No operation TRAP S/W Interrupt Wait For Interrupt (Low Pow- ...
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... ST72321M6 ST72321M9 INSTRUCTION SET OVERVIEW (Cont’d) 10.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an index register value ( with a pointer value located in memory. The point- er address follows the opcode ...
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... ST72321M6 ST72321M9 INSTRUCTION SET OVERVIEW (Cont’d) 10.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations ...
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... ST72321M6 ST72321M9 INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is true (1) CALL Call subroutine CALLR Call subroutine relative ...
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... ST72321M6 ST72321M9 INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the Stack RCF Reset carry flag RET Subroutine Return RIM ...
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... ST72321M6 ST72321M9 11 ELECTRICAL CHARACTERISTICS 11.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- ferred 11.1.1 Minimum and Maximum values Unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the ...
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... ST72321M6 ST72321M9 11.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- 11.2.1 Voltage Characteristics Symbol Supply voltage DD SS ...
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... ST72321M6 ST72321M9 11.2.3 Thermal Characteristics Symbol T Storage temperature range STG T Maximum junction temperature (see J 11.3 OPERATING CONDITIONS 11.3.1 General Operating Conditions Symbol Parameter f Internal clock frequency CPU Standard voltage range (except Flash Write/Erase Operating Voltage for Flash Write/Erase T Ambient temperature range A Figure 68. f Max Versus V ...
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... ST72321M6 ST72321M9 OPERATING CONDITIONS (Cont’d) 11.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for V Symbol Parameter Reset release threshold V IT+(LVD) (V rise) DD Reset generation threshold V IT-(LVD) (V fall LVD voltage threshold hysteresis V hys(LVD) 3) rise time ...
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... ST72321M6 ST72321M9 11.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consump- tion, the two current values must be added (except for Halt mode for which the clock is stopped). ...
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... ST72321M6 ST72321M9 SUPPLY CURRENT CHARACTERISTICS (Cont’d) 11.4.1.1 Power Consumption vs f Figure 69. Typical I in RUN mode DD 8MHz 9 4MHz 8 2MHz 1MHz 3.2 3.6 4 4.4 Vdd (V) Figure 70. Typical I in Slow mode DD 500kHz 1.20 250kHz 1.00 125kHz 62.5kHz 0.80 0.60 0.40 0.20 0.00 3.2 3.6 4 4.4 Vdd (V) 139/175 CPU Figure 71. Typical ...
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... ST72321M6 ST72321M9 SUPPLY CURRENT CHARACTERISTICS (Cont’d) 11.4.2 Supply and Clock Managers The previous current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consump- tion, the two current values must be added (except for Halt mode). ...
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... ST72321M6 ST72321M9 SUPPLY CURRENT CHARACTERISTICS (Cont’d) 11.4.3 On-Chip Peripherals Measured on LQFP64 generic board T Symbol Parameter I 16-bit Timer supply current DD(TIM) I ART PWM supply current DD(ART SPI supply current DD(SPI SCI supply current DD(SCI I2C supply current DD(I2C) I ADC supply current when converting ...
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... ST72321M6 ST72321M9 11.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for V 11.5.1 General Timings Symbol Parameter t Instruction cycle time c(INST) Interrupt reaction time t = Δt v(IT v(IT) c(INST) 11.5.2 External Clock Source Symbol Parameter V OSC1 input pin high level voltage OSC1H V OSC1 input pin low level voltage ...
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... ST72321M6 ST72321M9 CLOCK AND TIMING CHARACTERISTICS (Cont’d) 11.5.3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator oscillators. All the information given in this paragraph is based on characterization results with specified typical ex- ternal components. In the application, the resona- ...
Page 144
... ST72321M6 ST72321M9 CLOCK AND TIMING CHARACTERISTICS (Cont’d) f OSC Supplier (MHz Notes: 1. Resonator characteristics given by the ceramic resonator manufacturer. 2. SMD = [-R0: Plastic tape package ( LEAD = [-A0: Flat pack package (Radial taping Ho= 18 mm), -B0: Bulk mode is not recommended for 2 MHz resonator because the peak to peak amplitude is too small (>0.8 V) For more information on these resonators, please consult www ...
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... ST72321M6 ST72321M9 CLOCK CHARACTERISTICS (Cont’d) 11.5.4 RC Oscillators Symbol Parameter Internal RC oscillator frequency f OSC (RCINT) See Figure 74 Figure 74. Typical f OSC(RCINT) 4 3.8 3.6 3.4 3 (°C) A 145/175 Conditions T =25 ° Note: To reduce disturbance to the RC oscillator recommended to place decoupling capacitors between V Vdd = 5V Vdd = 5 ...
Page 146
... ST72321M6 ST72321M9 CLOCK CHARACTERISTICS (Cont’d) Note: 1. Data based on characterization results. 11.5.5 PLL Characteristics Symbol Parameter f PLL input frequency range OSC Δ Instantaneous PLL jitter CPU CPU Note: 1. Data characterized but not tested. The user must take the PLL jitter into account in the application (for example in serial communication or sampling of high frequency signals) ...
Page 147
... ST72321M6 ST72321M9 11.6 MEMORY CHARACTERISTICS 11.6.1 RAM and Hardware Registers Symbol Parameter V Data retention mode RM 11.6.2 Flash memory DUAL VOLTAGE HDFlash MEMORY Symbol Parameter f Operating frequency CPU V Programming voltage Supply current current Internal V stabilization time VPP PP t Data retention RET ...
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... ST72321M6 ST72321M9 11.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba- sis during product characterization. 11.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ...
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... ST72321M6 ST72321M9 EMC CHARACTERISTICS (Cont’d) 11.7.2 Electro Magnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/ 3 which specifies the board and the loading of each pin ...
Page 150
... ST72321M6 ST72321M9 EMC CHARACTERISTICS (Cont’d) 11.7.3 Absolute Maximum Ratings (Electrical Sensitivity) Based on three different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, re- fer to the application note AN1181. Absolute Maximum Ratings ...
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... ST72321M6 ST72321M9 11.8 I/O PORT PIN CHARACTERISTICS 11.8.1 General Characteristics Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis ...
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... ST72321M6 ST72321M9 I/O PORT PIN CHARACTERISTICS (Cont’d) 11.8.2 Output Driving Current Subject to general operating conditions for V Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 78 Output low level voltage for a high sink I/O pin ...
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... ST72321M6 ST72321M9 I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 81. Typical V vs 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 2.5 3 3.5 Vdd(V ) Figure 82. Typical V vs Ta= 14 0°C Ta=9 5° Ta=2 5°C Ta=-45 ° 2 Figure 83. Typical 5.5 5 4.5 4 3 2.5 3 3.5 4 Vdd(V) 153/175 ...
Page 154
... ST72321M6 ST72321M9 11.9 CONTROL PIN CHARACTERISTICS 11.9.1 Asynchronous RESET Pin Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys V Output low level voltage OL I Input current on RESET pin IO R Weak pull-up equivalent resistor ...
Page 155
... ST72321M6 ST72321M9 CONTROL PIN CHARACTERISTICS (Cont’d) Figure 84. RESET pin protection when LVD is enabled. Required EXTERNAL RESET 0.01μF Figure 85. RESET pin protection when LVD is disabled. Recommended for EMC V DD 0.01 μF USER EXTERNAL RESET CIRCUIT 0.01 μF Required Note 1: – The reset network protects the device against parasitic resets. ...
Page 156
... ST72321M6 ST72321M9 CONTROL PIN CHARACTERISTICS (Cont’d) 11.9.2 ICCSEL/V Pin PP Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH I Input leakage current L Note: 1. Data based on design simulation and/or technology characteristics, not tested in production. Figure 86. Two typical Applications with ICCSEL/V ...
Page 157
... ST72321M6 ST72321M9 11.10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for V Refer to I/O port characteristics for more details on the input/output alternate function characteristics (out- put compare, input capture, external clock, PWM output...). 11.10.1 8-Bit PWM-ART Auto-Reload Timer Symbol Parameter t PWM resolution time res(PWM) f ART external clock frequency ...
Page 158
... ST72321M6 ST72321M9 11.11 COMMUNICATION INTERFACE CHARACTERISTICS 11.11.1 SPI - Serial Peripheral Interface Subject to general operating conditions for and T unless otherwise specified. CPU A Symbol Parameter f SCK SPI clock frequency 1/t c(SCK) t r(SCK) SPI clock rise and fall time t f(SCK setup time su(SS hold time ...
Page 159
... ST72321M6 ST72321M9 COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 88. SPI Slave Timing Diagram with CPHA=1 SS INPUT t su(SS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 t w(SCKH) t a(SO) t w(SCKL) see MISO OUTPUT HZ note 2 t su(SI) MOSI INPUT Figure 89. SPI Master Timing Diagram SS INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 CPHA=1 CPOL=0 ...
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... ST72321M6 ST72321M9 COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) 2 11.11 Inter IC Control Interface Subject to general operating conditions for V , and T unless otherwise specified CPU Symbol Parameter t SCL clock low time w(SCLL) t SCL clock high time w(SCLH) t SDA setup time su(SDA) t SDA data hold time ...
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... ST72321M6 ST72321M9 COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) The following table gives the values to be written in the I2CCCR register to obtain the required I SCL line frequency. Table 26. SCL Frequency Table f SCL V = 4.1 V (kHz =3.3 kΩ R =4.7 kΩ 400 NA NA 300 NA NA 200 ...
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... ST72321M6 ST72321M9 11.12 10-BIT ADC CHARACTERISTICS Subject to general operating conditions for V Symbol Parameter f ADC clock frequency ADC V Analog reference voltage AREF V Conversion voltage range AIN Positive input leakage current for analog input I lkg Negative input leakage current on ro- 2 bust analog pins R External input impedance ...
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... ST72321M6 ST72321M9 ADC CHARACTERISTICS (Cont’d) Figure 91. R max AIN ADC (pF) PARASITIC Figure 93. Typical A/D Converter Application R AIN V AIN Notes represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca- PARASITIC pacitance (3 pF) ...
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... ST72321M6 ST72321M9 ADC CHARACTERISTICS (Cont’d) 11.12.1 Analog Power Supply and Reference Pins Depending on the MCU pin count, the package may feature separate V AREF power supply pins. These pins supply power to the A/D converter cell and function as the high and low reference voltages for the conversion. ...
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... ST72321M6 ST72321M9 10-BIT ADC CHARACTERISTICS (Cont’d) 11.12.3 ADC Accuracy 1) Conditions Symbol Parameter Total unadjusted error Offset error Gain Error Differential linearity error Integral linearity error L Notes: 1. ADC Accuracy vs. Negative Injection Current: Injecting negative current may reduce the accuracy of the conversion being performed on another analog input ...
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... ST72321M6 ST72321M9 12 PACKAGE CHARACTERISTICS 12.1 ECOPACK In order to meet environmental requirements, ST offers these devices in different grades of ECO- PACK® packages, depending on their level of en- vironmental compliance. ECOPACK® specifica- 12.2 PACKAGE MECHANICAL DATA Figure 96. 80-Pin Low Profile Quad Flat Package D D1 12.3 THERMAL CHARACTERISTICS Symbol ...
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... ST72321M6 ST72321M9 13 ST72321Mx DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user pro- grammable versions (Flash). 13.1 FLASH OPTION BYTES STATIC OPTION BYTE 0 7 WDG 1 Default The option bytes allow the hardware configuration of the microcontroller to be selected. They have no ...
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... ST72321M6 ST72321M9 ST72321Mx DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d) OPT2 = Reserved, must be kept at default value. OPT1= PKG0 Package selection bit 0 This option bit is used to select the package (see table in PKG1 option bit description). OPT0= FMP_R Flash memory read-out protection Read-out protection, when selected, provides a ...
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... ST72321M6 ST72321M9 ST72321xx DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d) 13.2 DEVICE ORDERING INFORMATION Figure 97. Ordering information scheme Example: Family ST7 microcontroller family Memory type F: Flash Sub-family 321 (Flash) No. of pins Memory size Kbytes Kbytes Package T = LQFP Temperature range 6 = -40 ° ...
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... ST72321M6 ST72321M9 14 KNOWN LIMITATIONS 14.1 Safe Connection of OSC1/OSC2 Pins The OSC1 and/or OSC2 pins must not be left un- connected otherwise the ST7 main oscillator may start and, in this configuration, could generate an f clock frequency in excess of the allowed OSC maximum (>16 MHz.), putting the ST7 in an un- safe/undefined state ...
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... ST72321M6 ST72321M9 LD A,sema ; check the semaphore status if edge is detected CP A,#01 jrne OUT call call_routine; call the interrupt routine OUT:LD A,#00 LD sema,A .call_routine ; entry to call_routine PUSH A PUSH X PUSH CC .ext1_rt ; entry to interrupt routine LD A,#00 LD sema,A IRET Case 2: Writing to PxOR or PxDDR with Global In- terrupts Disabled: SIM ...
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... ST72321M6 ST72321M9 – The interrupt flag is cleared in any part of the code while this interrupt is disabled If these conditions are not met, the symptom can be avoided by implementing the following se- quence: PUSH CC SIM reset interrupt flag POP CC 14.6 SCI Wrong Break duration Description A single break character is sent by setting and re- setting the SBK bit in the SCICR2 register ...
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... ST72321M6 ST72321M9 in ICC mode. Once in ICC mode, the ICC protocol enables an ST7 microcontroller to communicate with an external controller (such as a PC). ICC mode is entered by applying 39 pulses on the IC- CDATA signal during reset. To enter ICC mode, the device goes through other modes, some modes are critical because the I/Os PG[7:0] and PH[7:0] are forced to output push-pull ...
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... ST72321M6 ST72321M9 15 REVISION HISTORY Table 27. Revision History Date Revision 26-Sep-2006 1 Initial release Modified title of the document Removed references to ROM devices Modified HDFlash endurance and data retention on first page Modified Added note 2 to Modified Modified t Modified V ESD(MM) Modified 04-May-2009 2 Modified conditions for V ity)” ...
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... ST72321M6 ST72321M9 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...