ST72321R6-Auto STMicroelectronics, ST72321R6-Auto Datasheet - Page 49

• Manufacturer Part Number: ST72321R6-Auto
• Description: 8-bit MCU for automotive with 32 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321R6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

ST72321xx-Auto
7
7.1
7.2
Note:
Interrupts
Introduction
The ST7 enhanced interrupt management provides the following features:
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This interrupt management is based on:
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This enhanced interrupt controller guarantees full upward compatibility with the standard
(not nested) ST7 interrupt controller.
Masking and processing flow
The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx
registers which give the interrupt software priority level of each interrupt vector (see
15). The processing flow is shown in
When an interrupt request has to be serviced:
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The interrupt service routine should end with the IRET instruction which causes the
contents of the saved registers to be recovered from the stack.
As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
Hardware interrupts
Software interrupt (TRAP)
Nested or concurrent interrupt management with flexible interrupt priority and level
management:
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–
–
–
Bit 5 and bit 3 of the CPU CC register (I1:0)
Interrupt software priority registers (ISPRx)
Fixed interrupt vector addresses located at the high addresses of the memory map
(FFE0h to FFFFh) sorted by hardware priority order
Normal processing is suspended at the end of the current instruction execution.
The PC, X, A and CC registers are saved onto the stack.
I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx
registers of the serviced interrupt vector.
The PC is then loaded with the interrupt vector of the interrupt to service and the first
instruction of the interrupt service routine is fetched (refer to
mapping
Up to 4 software programmable nesting levels
Up to 16 interrupt vectors fixed by hardware
2 non-maskable events: RESET, TRAP
1 maskable Top Level event: TLI
for vector addresses).
Doc ID 13829 Rev 1
Figure
17.
Table 20: Interrupt
Interrupts
Table
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