TDA18271HD/C2,557 NXP Semiconductors, TDA18271HD/C2,557 Datasheet

IC TV SILICON TUNER 64-HLQFN

TDA18271HD/C2,557

Manufacturer Part Number
TDA18271HD/C2,557
Description
IC TV SILICON TUNER 64-HLQFN
Manufacturer
NXP Semiconductors
Type
Silicon Tunerr
Datasheets

Specifications of TDA18271HD/C2,557

Applications
Set-Top Boxes
Mounting Type
Surface Mount
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935285058557
TDA18271HD/C2
TDA18271HD/C2
1. General description
2. Features
3. Applications
3.1 Target applications
The TDA18211HD is a Silicon Tuner IC designed for digital terrestrial (DVB-T) TV
reception. The TDA18211HD integrates the overall tuning function, including selectivity,
and provides a low-IF output signal.
The TDA18211HD uses integrated IF filters to support 6/7/8 MHz channel bandwidths.
The TDA18211HD requires only one single 16 MHz crystal for clock generation. A clock
signal is available on crystal oscillator output pins (XTOUTP/XTOUTN) to synchronize the
channel decoder and slave front end in case of DVR configuration.
This specification is based on software version 3.4
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TDA18211HD
DVB-T Silicon Tuner IC
Rev. 05 — 2 June 2009
Fully integrated RF tracking filters for unwanted signal suppression
Fully integrated IF selectivity (no need for external SAW filters)
Fully integrated oscillators with no external components
Integrated wideband gain control
Alignment free
RF loop-through for easy implementation in the STB
Input power level indicator
Integrated die thermal sensor
Single 3.3 V power supply
Low power consumption (780 mW)
Crystal oscillator output buffer (16 MHz) to allow single crystal applications
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Three Standby modes
RoHS packaging
DVB-T Set-Top-Box (STB) and TV receiver
Application optimization is described in the application notes
2
C-bus interface compatible with 3.3 V and 5 V microcontrollers
Product data sheet

Related parts for TDA18271HD/C2,557

TDA18271HD/C2,557 Summary of contents

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TDA18211HD DVB-T Silicon Tuner IC Rev. 05 — 2 June 2009 1. General description The TDA18211HD is a Silicon Tuner IC designed for digital terrestrial (DVB-T) TV reception. The TDA18211HD integrates the overall tuning function, including selectivity, and provides a ...

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... NXP Semiconductors 3.2 Key benefits I The TDA18211HD is a low cost Silicon Tuner targeting digital terrestrial applications. The TDA18211HD matches the performance of the conventional can tuners while reducing the size of the tuner function drastically. Additionally, the following benefits can be stated: ...

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... NXP Semiconductors 6. Block diagram AGC CONTROL LNA 10 RF_IN ATTENUATORS AGC1 AGC2 15 STO 13 LT TDA18211HD INTERFACE 32 AS Fig 1. Block diagram TDA18211HD_5 Product data sheet DC-to-DC CONVERTER LC RF tracking polyphase filters filter RF AGC TEST SIGNAL GENERATOR CONTROL CALIBRATION SYNTHESIZER VT_CAL CP_CAL SCL SDA Rev. 05 — ...

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... NXP Semiconductors 7. Pinning information 7.1 Pinning terminal 1 index area CAPRFAGC Fig 2. 7.2 Pin description Table 3. Symbol GND n.c. VCC RF_IN GND CAPRFAGC LT TDA18211HD_5 Product data sheet GND 1 GND 2 GND 3 GND 4 GND 5 GND 6 GND 7 n.c. 8 TDA18211HD VCC 9 RF_IN 10 GND GND 14 STO 15 VCC ...

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... NXP Semiconductors Table 3. Symbol GND STO VCC CAPREGVCO VCC MASTERSYNC CAPFILTVCO VT_COARSE VT_FINE GND CP_LO GND XTALP XTALN FREEZE XTOUT_MS XTOUTP XTOUTN AS VCC CP_CAL VT_CAL GND SCL SDA CAPREG18 GND CAPREG28 GND VCC IFOUTN IFOUTP V_IFAGC GND VSYNC CAPREGFILTRF GND - TDA18211HD_5 ...

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... NXP Semiconductors 8. Functional description The RF input signal is driven to a low-noise amplifier then band-pass filtered, amplified and fed to the image rejection mixer. The mixer downconverts the RF signal to a low IF, which depends on channel bandwidth (standard IF filters are implemented for 6/7/8 MHz channel bandwidths; see The gain between the antenna pin (pin RF_IN) and the loop-through pin (pin LT ...

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... NXP Semiconductors 8.3 Crystal input mode The TDA18211HD requires a 16 MHz crystal reference. The chosen crystal must withstand at least 100 W drive level. An additional shunt capacitor as shown in is also needed. Its typical value is 5.6 pF. The quartz references for which performance is guaranteed are: • ...

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Table 5. I C-bus format Name Byte Sub name address 7 Address byte Address byte byte ID 00h 1 Thermo byte TM 01h POR Power level byte PL 02h Easy ...

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Table 5. I C-bus format …continued Name Byte Sub name address 7 Extended byte 7 EB7 16h Extended byte 8 EB8 17h CID_ALARM Extended byte 9 EB9 18h Extended byte 10 EB10 19h Extended byte 11 EB11 1Ah Extended ...

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... NXP Semiconductors 2 9.2 I C-bus at power-on reset 2 Table 6. I C-bus at power-on reset Name Byte Address byte 1 - Address byte byte ID Thermo byte TM Power Level byte PL Easy Prog byte 1 EP1 Easy Prog byte 2 EP2 Easy Prog byte 3 EP3 Easy Prog byte 4 EP4 Easy Prog byte 5 ...

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... NXP Semiconductors 2 Table 6. I C-bus at power-on reset Name Byte Extended byte 21 EB21 Extended byte 22 EB22 Extended byte 23 EB23 [1] X indicates a bit not changed on reset. 9.3 Description of symbols used Table 7. I C-bus registers bits explanation Address Byte Symbol MA[1:0] AD[5:0] Data bytes ...

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... NXP Semiconductors 2 Table 7. I C-bus registers bits explanation Address Byte Symbol 09h CD1 CAL_DIV[22:16] 0Ah CD2 CAL_DIV[15:8] 0Bh CD3 CAL_DIV[7:0] 0Ch MPD IF_NOTCH MAIN_POST_DIV[6:0] LO synthesizer post-divider bits 0Dh MD1 MAIN_DIV[22:16] 0Eh MD2 MAIN_DIV[15:8] 0Fh MD3 MAIN_DIV[7:0] Extended bytes 10h EB1 CALVCO_FORLON ...

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... NXP Semiconductors 2 9.3.1 I C-bus address selection The module address contains programmable address bits (MA[1:0]), which offer the possibility to have several synthesizers ( one system by applying a specific voltage on the AS input (V Table 8. Legend: * power-on reset value Bit Table 9. Legend: * power-on reset value Bit ...

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... NXP Semiconductors Table 11. Legend: * power-on reset value Bit Symbol 5 TM_RANGE R/W 4 TM_ON TM_D[3:0] 9.3.4 Description of power level byte (read mode) There are 9 power level bits, dispatched in byte 2 and 3. They indicate the composite voltage gain of the LNA, the loaded attenuator voltage gain, and the level at the input of the RF AGC ...

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... NXP Semiconductors 9.3.5 Description of Easy Prog byte 1 Table 13. Legend: * power-on reset value Bit BP_FILTER[2:0] 9.3.6 Description of Easy Prog byte 2 Table 14. Legend: * power-on reset value Bit RF_BAND[2: GAIN_TAPER[4:0] 9.3.7 Description of Easy Prog byte 3 The TDA18211HD has three different Standby modes. Two Standby modes are dedicated to special application demands ...

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... NXP Semiconductors Table 16. Bit [1] In all modes, the I 9.3.8 Description of Easy Prog byte 4 Table 17. Legend: * power-on reset value Bit Symbol 7 FM_RFN 6 XTOUT_ON IF_LEVEL[2: CAL_MODE[1:0] R recommended to follow the flowcharts described in any calibration, as they require a precise set of sequential operations. The further comments can only give an overview of what is typically done during the flowchart. ...

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... NXP Semiconductors The image rejection calibration consists in optimizing some tunable parameters inside the mixer throughout a set of internal measurements, leading to ensure typical value of image rejection. The internal signal used during this phase is generated by the PLL calibration (CAL PLL). The RF tracking filters central frequency can be adjusted with the tuning word RFC_CPROG. The RF tracking fi ...

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... NXP Semiconductors 9.3.12 Description of Main Post-Divider byte Table 21. Legend: * power-on reset value Bit 9.3.13 Description of Main divider bytes 1, 2 and 3 Table 22. Legend: * power-on reset value Address Register Bit 0Dh 0Eh 0Fh TDA18211HD_5 Product data sheet MPD - Main Post-Divider byte (subaddress 0Ch) bit description ...

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... NXP Semiconductors 9.3.14 Description of Extended bytes Table 23. EB1 to EB23 - Extended bytes (address 10h to 26h) bit description Legend: * power-on reset value Address Register Bit 10h EB1 11h EB2 12h EB3 13h EB4 14h EB5 7 and 6 EB5[7:0] 15h EB6 16h EB7 7 and 6 EB7[7:6] ...

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... NXP Semiconductors Table 23. EB1 to EB23 - Extended bytes (address 10h to 26h) bit description Legend: * power-on reset value Address Register Bit 1Ah EB11 1Bh EB12 7 and 6 EB12[7: 1Ch EB13 and 2 RFC_M[1: 1Dh EB14 1Eh EB15 1Fh EB16 20h EB17 21h EB18 and 0 AGC1_GAIN[1:0] ...

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... NXP Semiconductors Table 23. EB1 to EB23 - Extended bytes (address 10h to 26h) bit description Legend: * power-on reset value Address Register Bit 24h EB21 and 0 AGC2_GAIN[1:0] 25h EB22 26h EB23 Table 24. FORCELP_FC2_EN TDA18211HD_5 Product data sheet Symbol Access AGC2_LOOP_OFF R/W EB21[6:2] R/W R/W EB22[7] ...

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... NXP Semiconductors 2 9.4 I C-bus programming flowcharts The following flowcharts describe how to: • Initialize the TDA18211HD • Launch the calibrations • Normal mode The image rejection calibration as well as RF tracking filters calibration must be launched the way explicitly described in the flowchart. If not done this way, it may result in bad ...

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... NXP Semiconductors 2. Update at the same moment is indicated by separation with commas: IR_GSTEP, I2C_XTOUT_ASYM and PD_AGC1_DET are updated registers update C-bus registers update of the bytes EP5, EB12 and EB13 4. Bytes EP1 to CD2 are written in a single I Example: Start C0 03 EP1 EP2 EP3 EP4 EP5 CPD CD1 CD2 Stop 5 ...

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... NXP Semiconductors a. General description to find a value in a table b. Example to find the value RFC_K corresponding to f Fig 6. Units • In the flowcharts, hexadecimal values end with “h”, decimal values with “d” • Frequency variables used in computations are expressed in kHz, for example 1 GHz is written as 1000000 ...

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... NXP Semiconductors 9.4.2 Flowchart TDA18211SetRf_dual Table 25. Function Description Input Table Output The initialization phase has to be launched before any SetRf master is selected for the channel configuration slave is selected for the channel configuration. Fig 7. TDA18211HD_5 Product data sheet TDA18211SetRf_dual Description ...

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... NXP Semiconductors 9.4.3 Flowchart TDA18211InitCal Table 26. Function Description Input Table Output Fig 8. TDA18211HD_5 Product data sheet TDA18211InitCal Description systematic initialization for master and slave tuners MS_init - TMVALUE_RFCAL, init_done Start TDA18211InitCal MS_init = 1 Master initialization initialization sequence Call TDA18211FixedContentsI2Cupdate MS_init Calibrate the RF tracking filters ...

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... NXP Semiconductors 9.4.4 Flowchart TDA18211FixedContentsI2Cupdate Table 27. Function Description Input Table Output Start MS TDA18211FixedContentsI2Cupdate 2 Actions Internal table I C-bus Internal table update with TM = 08h - correct values PL = 80h - EP1 = C6h - EP2 = DFh - EP3 = 16h - EP4 = 60h - EP5 = 80h - CPD = 80h - CD1 = 00h - CD2 = 00h ...

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... NXP Semiconductors 9.4.5 Flowchart TDA18211CalcRFFilterCurve Table 28. Function Description Input Table Output f RF(max RF(max) f RF(max) Fig 10. Flowchart TDA18211CalcRFFilterCurve TDA18211HD_5 Product data sheet TDA18211CalcRFFilterCurve Description calculate the RF filter curves coefficients RF1_default, RF2_default, RF3_default, MS RF_BAND_map TMVALUE_RFCAL Start TDA18211CalcRFFilterCurve Wait 200 ms for die temperature stabilization ...

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... NXP Semiconductors 9.4.6 Flowchart TDA18211RFTrackingFiltersInit Table 29. Function Description Input Table Output bcal is a boolean output from TDA18211PowerScan: bcal = 1 (true): enables the calibration of the RF tracking filters bcal = 0 (false): no calibration is performed, default values for RFC_CPROG are used TDA18211HD_5 Product data sheet TDA18211RFTrackingFiltersInit Description calculate the RF fi ...

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... NXP Semiconductors Fig 11. Flowchart TDA18211RFTrackingFiltersInit TDA18211HD_5 Product data sheet TDA18211RFTrackingFiltersInit RF_A1 = 0, RF_B1 = 0, RF_A2 = 0, RF_B2 = 0 RF1_default Find RF1_default, RF2_default, RF3_default = f Look for optimized calibration frequency MS Call TDA18211PowerScan MS Find Cprog_cal1 to track RF1 RF1 Call TDA18211CalibrateRF RF1 Find Cprog_table = f in RF_CAL_map RF(max) RF_CAL_map Cprog_cal1 = Cprog_table1 ...

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... NXP Semiconductors 9.4.7 Flowchart TDA18211PowerScanInit Table 30. Function Description Input Table Output Actions Set standard mode to digital mode Tuner registers update Set AGC1_GAIN Set AGC2_GAIN 1.5 MHz low-pass filter Tuner register update Fig 12. Flowchart TDA18211PowerScanInit 9.4.8 Flowchart TDA18211PowerScan Table 31. Function Description Input ...

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... NXP Semiconductors RF_BAND_map RF_CAL_map CID_TARGET_map MS freq_input freq_MAINPLL freq_input sgn count freq_input freq_MAINPLL count freq_MAINPLL Fig 13. Flowchart TDA18211PowerScan TDA18211HD_5 Product data sheet Start TDA18211PowerScan Actions Find RF_BAND = f in RF_BAND_map(MS) RF(max) Find Cprog_table = f in RF_CAL_map RF(max) Find GAIN_TAPER = f in GAIN_TAPER_map RF(max) Find CID_TARGET count_limit = f ...

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... NXP Semiconductors 9.4.9 Flowchart TDA18211CalibrateRF Table 32. Function Description Input Table Output TDA18211HD_5 Product data sheet TDA18211CalibrateRF Description find the Cprog for which freq_input is the central frequency of the RF tracking filters freq_input, MS BP_FILTER_map, KM_map, GAIN_TAPER_map RFC_CPROG Rev. 05 — 2 June 2009 TDA18211HD DVB-T Silicon Tuner IC Reference Table 42 “ ...

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... NXP Semiconductors Actions Normal mode Switch OFF AGC1 Set AGC1_GAIN Frequency dependent parameters update Find BP_FILTER = f BP_FILTER_map Find GAIN_TAPER = f KM_map Find RF_BAND = f GAIN_TAPER_map Find RFC_K, RFC_M = f freq_input Tuner registers update MS MAIN PLL charge pump source CAL PLL charge pump source Force DCDC converter ...

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... NXP Semiconductors 9.4.10 Flowchart TDA18211MSPOR Table 33. Function Description Input Table Output Actions Power up Detector 1 Turn AGC1 loop ON Set AGC1_GAIN Set AGC2_GAIN POR mode 1.5 MHz low-pass filter disabled Fig 15. Flowchart TDA18211MSPOR 9.4.11 Flowchart TDA18211RFtrackingFiltersCorrection Table 34. Function Description Input Table Output TDA18211HD_5 ...

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... NXP Semiconductors RF_CAL_map RF_BAND_map freq_input MS RF_A2 Capprox = RF2 RF_A2 RF_B2 RF_B2 + Cprog_table Cprog_table freq_input RF_CAL_DC_OVER_DT_map freq_input dCoverdT TMVALUE_CURRENT TMVALUE_RFCAL Capprox RFCAL_TCOMP Fig 16. Flowchart TDA18211RFtrackingFiltersCorrection TDA18211HD_5 Product data sheet Start TDA18211RFTrackingFiltersCorrection Action Power up TDA18211 Read die current temperature Call TDA18211ThermometerRead Frequency dependant parameters update ...

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... NXP Semiconductors 9.4.12 Flowchart TDA18211ChannelConfiguration Table 35. Function Description Input Table Output TDA18211HD_5 Product data sheet TDA18211ChannelConfiguration Description tune the tuner according to the channel and broadcast configuration freq_input, MS, Standard STANDARD_DESCRIPTION_map, BP_FILTER_map, RF_BAND_map, CAL_PLL_map, GAIN_TAPER_map, IR_MEAS_map - Rev. 05 — 2 June 2009 ...

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Start TDA18211ChannelConfiguration Actions Standard mode update Update TV broadcast parameters Switch RFAGC to high speed mode Standard Normal mode Update IF output level Update IF notch frequency STANDARD_DESCRIPTION_ Update extended byte 22 map Update IF center frequency IR_MEAS_map Disable power ...

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... NXP Semiconductors 9.4.13 Flowchart TDA18211CalcMAINPLL Table 36. Function Description Input Table Output MPD, MD1, MD2 and MD3 are 8-bit registers. Arithmetical and logical operations performed on those registers are considered binary operations. (Dividing is right shifting and multiplying is left shifting, etc.) MAIN_PLL_map Find MAIN_POST_DIV, Div = f ...

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... NXP Semiconductors 9.4.14 Flowchart TDA18211CalcCALPLL CPD, CD1, CD2 and CD3 are 8-bit registers. Arithmetical and logical operations performed on those registers are considered binary operations. Dividing is right shifting and multiplying is left shifting. Table 37. Function Description Input Table Output CAL_PLL_map Find CAL_POST_DIV, Div = f ...

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... NXP Semiconductors 9.4.15 Flowchart TDA18211ThermometerRead Table 38. Function Description Input Table Output Actions Switch thermometer ON Read thermometer information Call TDA18211Read no Switch TM_RANGE Wait temperature sensing Read thermometer information Call TDA18211Read TM_D Find TMVALUE = f(TM_D, TM_RANGE) in TM_RANGE THERMOMETER_map Switch thermometer OFF Normal mode Fig 20 ...

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... NXP Semiconductors 9.4.16 Flowchart TDA18211Read Table 39. Function Description Input Table Output The software internal table registers are not updated throughout a read procedure. The update is performed at the level of the call TDA18211Read. Fig 21. Flowchart TDA18211Read TDA18211HD_5 Product data sheet TDA18211Read Description read the 16 first bytes of the TDA18211HD ...

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... NXP Semiconductors 9.4.17 Flowchart TDA18211ReadExtended Table 40. Function Description Input Table Output The software internal table registers are not updated throughout a read procedure. The update is performed at the level of the call TDA18211ReadExtended. Fig 22. Flowchart TDA18211ReadExtended 9.5 Maps Table 41. Standard ATSC 6 MHz DVB-T 6 MHz ...

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... NXP Semiconductors Table 43. RF_BAND_map f RF_BAND Used in flowchart RF(max) (kHz) [2:0] RF_A1 203500 100 RF_A1_4 RF_B1_4 RF_A2_4 RF_B2_4 RF1_4 0 457800 101 RF_A1_5 RF_B1_5 RF_A2_5 RF_B2_5 RF1_5 RF2_5 RF3_5 230000 865000 110 RF_A1_6 RF_B1_6 RF_A2_6 RF_B2_6 RF1_6 RF2_6 RF3_6 489500 Table 44. f RF(max) ...

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... NXP Semiconductors Table 46. f LO(max) 175750 195250 219750 251250 270500 293000 319500 351500 390500 439500 502500 541000 586000 639000 703000 781000 879000 [1] Used in Table 47. f RF(max 175800 181300 186900 192400 198000 203500 - - - - - - - - - - - TDA18211HD_5 Product data sheet CAL_PLL_map (kHz) CAL_POST_DIV[7:0] BAh B9h ...

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... NXP Semiconductors Table 47. f RF(max [1] The gain taper function compensates for any systematic RF gain ripple and makes it flat versus frequency. Table 48. RF_CAL_DC_OVER_DT_map [1] f (kHz) dCoverdT f RF(max) RF(max) 203500 32h 417000 353000 19h 419000 356000 1Ah 422000 359000 1Bh 424000 363000 1Ch ...

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... NXP Semiconductors Table 49. RF_CAL_map f Cprog_ f Cprog_ RF(max) RF(max) (kHz) table (kHz) table 174000 18h 267000 29h 175000 1Ah 269000 2Ah 176000 1Bh 271000 2Bh 178000 1Dh 273000 2Ch 179000 1Eh 275000 2Dh 180000 1Fh 277000 2Eh 181000 20h 279000 2Fh 182000 ...

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... NXP Semiconductors Table 49. RF_CAL_map …continued f Cprog_ f Cprog_ RF(max) RF(max) (kHz) table (kHz) table 236000 1Bh 355000 51h 237000 1Ch 357000 52h 240000 1Dh 359000 53h 242000 1Eh 361000 54h 244000 1Fh 362000 55h 247000 20h 364000 56h 249000 21h 368000 57h ...

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... NXP Semiconductors Table 51. f RF(max) 200 600 865 Table 52. f RF(max) 186250 230000 345000 426000 489500 697500 842000 10. Internal circuitry Table 53. Symbol RF_IN CAPRFAGC LT TDA18211HD_5 Product data sheet IR_MEAS_map (kHz) CID_TARGET_map CID_Target Internal circuits [1] Pin Description Rev. 05 — 2 June 2009 TDA18211HD ...

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... NXP Semiconductors Table 53. Symbol STO CAPREGVCO MASTERSYNC CAPFILTVCO VT_COARSE VT_FINE CP_LO TDA18211HD_5 Product data sheet Internal circuits …continued [1] Pin Description Rev. 05 — 2 June 2009 TDA18211HD DVB-T Silicon Tuner IC Average DC voltage 0.85 V 001aaf840 2.8 V (Normal mode (Standby mode) 001aaf841 0 001aaf842 1.6 V (Normal mode) ...

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... NXP Semiconductors Table 53. Symbol XTALP XTALN FREEZE XTOUT_MS XTOUTP XTOUTN TDA18211HD_5 Product data sheet Internal circuits …continued [1] Pin Description Rev. 05 — 2 June 2009 TDA18211HD DVB-T Silicon Tuner IC Average DC voltage 1.45 V 001aaf847 1.45 V 001aaf848 3.3 V 001aaf849 high-Z 001aaf850 2.4 V 001aaf851 2.4 V 001aaf852 © ...

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... NXP Semiconductors Table 53. Symbol AS CP_CAL VT_CAL SCL SDA CAPREG18 CAPREG28 TDA18211HD_5 Product data sheet Internal circuits …continued [1] Pin Description Rev. 05 — 2 June 2009 TDA18211HD DVB-T Silicon Tuner IC Average DC voltage high-Z 001aaf853 3.3 V (Normal mode) 0 mode) 001aaf854 3.3 V (Normal mode) 0 001aaf855 mode) ...

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... NXP Semiconductors Table 53. Symbol IFOUTN IFOUTP V_IFAGC VSYNC CAPREGFILTRF [1] ESD protection components are not shown. 11. Limiting values Table 54. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol stg esd [1] The TDA18211HD withstands the latch-up specifications of JEDEC (JESD78A), with the specific recommendation using coupling capacitors on pins RF_IN, LT, STO, XTOUTP and XTOUTN ...

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... NXP Semiconductors 12. Thermal characteristics Table 55. Symbol R th(j-c) [1] The junction temperature can be obtained with the formula T the thermal resistance of the application. R maximum value defined in 13. Characteristics All data in this section refers to Master mode operation. Table 56 amb Symbol f RF(lt) VSWR G v(lt CSO CTB ...

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... NXP Semiconductors Table 57 amb Symbol f RF(STO) Z o(STO) G v(STO) Table 58 amb for test circuit see Symbol Supply amb Input f RF VSWR NF tun G v(tun)max G AGC(tun) V i(max) V L(tun-RF) TDA18211HD_5 Product data sheet Slave tuner output characteristics (pin STO) = 3.3 V; for test circuit see Figure ...

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... NXP Semiconductors Table 58 amb for test circuit see Symbol Output V o(IF)dif(p-p) Z o(IF) G AGC(IF) G tlt f IF(stpb)lp image t ripple n IF Various t startup(tun) t set S dig [1] Measured with TDA10048HN channel decoder. TDA18211HD_5 Product data sheet General characteristics for TV reception (RF input to IF output output level option = 2 V (p-p); IF output load = each terminal; ...

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... NXP Semiconductors Table 59 amb otherwise specified. Symbol IF AGC input: pin V_IFAGC V AGC /dV AGC Crystal oscillator f xtal Z i Crystal oscillator output buffer; pins XTOUTP and XTOUTN o(p- C-bus Pin SCL SCL Pin SDA [1] Devices that use non-standard supply voltages, which do not conform the intended I must relate their input levels to the supply voltage to which the pull-up resistors are connected ...

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... NXP Semiconductors (dBc/Hz) (1) Offset is 1 kHz. (2) Offset is 10 kHz. (3) Offset is 100 kHz. Fig 23. Typical phase noise curve Selectivity (dB) (1) 6 MHz bandwidth filter. (2) 7 MHz bandwidth filter. (3) 8 MHz bandwidth filter. (4) 9 MHz bandwidth filter. Fig 24. Typical IF selectivity curves TDA18211HD_5 Product data sheet ...

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... NXP Semiconductors 14. Application information 14.1 Application example TV Fig 25. Example for TDA18211HD of DVB-T dual-tuner reception 14.2 Application notes Please contact the NXP sales office for additional information on dual-tuner DVB-T applications. TDA18211HD_5 Product data sheet XTAL RF RF_IN SURGE PROTECTION SILICON TUNER TDA18211 RF LTO ...

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VCC3.3 4 VCC3.3 SDA SDA 3 GND 2 SCL 1 SCL R1 R2 2.2 2 VCC3.3 GND 1 GND 2 GND 3 VCC1 GND 4 GND 5 C128 GND GND 7 n.c. ...

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... NXP Semiconductors 16. Package outline HLQFN64R; plastic thermal enhanced low profile quad flat package; no leads; 64 terminals; resin based; body 9 terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.3 9.1 2.92 mm 1.7 0.2 8.9 2.82 OUTLINE VERSION IEC ...

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... NXP Semiconductors 17. Printed-circuit board 17.1 Reflow profile See application note AN10366 . 17.2 Desoldering recommendation See application notes AN10366 . TDA18211HD_5 Product data sheet Rev. 05 — 2 June 2009 TDA18211HD DVB-T Silicon Tuner IC © NXP B.V. 2009. All rights reserved ...

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... NXP Semiconductors 17.3 Footprint layout C 0. solder lands solder paste solder resist occupied area DIMENSIONS 0.500 9.000 9.000 7.880 7.880 Fig 28. Footprint HLQFN64R (SOT903-1) TDA18211HD_5 Product data sheet 1 0.555 0.250 9.500 9.500 4.610 Rev. 05 — 2 June 2009 TDA18211HD DVB-T Silicon Tuner IC ...

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... NXP Semiconductors 18. Abbreviations Table 60. Acronym AGC DVB-T DVR ESD IF LNA LO PLL QAM RoHS SAW STB VCO 19. Revision history Table 61. Revision history Document ID Release date TDA18211HD_5 20090602 • Modifications: Figure 21 “Flowchart TDA18211Read” TDA18211HD_4 20090505 TDA18211HD_3 20080304 TDA18211HD_2 20071121 TDA18211HD_1 20070802 ...

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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

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... NXP Semiconductors 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3.1 Target applications . . . . . . . . . . . . . . . . . . . . . . 1 3.2 Key benefi Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Functional description . . . . . . . . . . . . . . . . . . . 6 8.1 Master and slave operation ...

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