DS22EV5110SQX/NOPB National Semiconductor, DS22EV5110SQX/NOPB Datasheet - Page 14

IC EQUAL DVI HDMI RETIMER 48-LLP

DS22EV5110SQX/NOPB

Manufacturer Part Number
DS22EV5110SQX/NOPB
Description
IC EQUAL DVI HDMI RETIMER 48-LLP
Manufacturer
National Semiconductor
Type
Equalizerr
Datasheet

Specifications of DS22EV5110SQX/NOPB

Applications
HDMI, DVI, Receivers
Mounting Type
Surface Mount
Package / Case
48-LLP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DS22EV5110SQX
www.national.com
General Recommendations
The DS22EV5110 is a high performance circuit capable of
delivering excellent performance. To achieve optimal perfor-
mance, careful attention must be paid to the details associ-
ated with high-speed design as well as providing a clean
power supply. Refer to the LVDS Owner’s Manual for more
detailed information on high-speed design tips as well as
many other available resources addressing signal integrity
design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL
PAIRS
The TMDS differential inputs and outputs must have a con-
trolled differential impedance of 100 Ω. It is preferable to route
TMDS lines exclusively on one layer of the board, particularly
for the input traces. The use of vias should be avoided if pos-
sible. If vias must be used, they should be used sparingly and
must be placed symmetrically for each side of a given differ-
ential pair. Route the TMDS signals away from other signals
and noise sources on the printed circuit board. All traces of
TMDS differential inputs and outputs must be equal in length
to minimize intra-pair skew.
LLP FOOTPRINT RECOMMENDATIONS
See National application note: AN-1187, “Leadless Lead-
frame Package (LLP)” for additional information on LLP pack-
ages footprint and soldering information.
FIGURE 11. Equivalent Output Structure
FIGURE 12. Equivalent Input Structure
14
POWER SUPPLY BYPASSING
Two
DS22EV5110 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be
connected to power planes routed on adjacent layers of the
printed circuit board. The layer thickness of the dielectric
should be minimized so the VDD and GND planes create a
low inductance supply with distributed capacitance. Second,
careful attention to supply bypassing through the proper use
of bypass capacitors is required. A 0.1 μF bypass capacitor
should be connected to each VDD pin such that the capacitor
is placed as close as possible to the DS22EV5110. Smaller
body size capacitors can help facilitate proper component
placement. Additionally, two capacitors with capacitance in
the range of 2.2 μF to 10 μF should be incorporated in the
power supply bypassing design as well. These capacitors can
be either tantalum or an ultra-low ESR ceramic and should be
placed as close as possible to the DS22EV5110.
EQUIVALENT I/O STRUCTURES
Figure 14 shows the DS22EV5110 CML output structure and
ESD protection circuitry.
Figure 15 shows the DS22EV5110 CML input structure and
ESD protection circuitry.
approaches
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