74LVC245ABQ,115 NXP Semiconductors, 74LVC245ABQ,115 Datasheet

IC TRANSCVR TRI-ST 8BIT 20QFN

74LVC245ABQ,115

Manufacturer Part Number
74LVC245ABQ,115
Description
IC TRANSCVR TRI-ST 8BIT 20QFN
Manufacturer
NXP Semiconductors
Series
74LVCr
Datasheet

Specifications of 74LVC245ABQ,115

Logic Type
Transceiver, Non-Inverting
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
Number Of Elements
1
Number Of Bits Per Element
8
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
74LVC
Number Of Channels Per Chip
8
Input Level
LVTTL
Output Level
LVTTL
Output Type
3-State
High Level Output Current
- 24 mA
Low Level Output Current
24 mA
Propagation Delay Time
2.9 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.2 V
Maximum Operating Temperature
+ 125 C
Function
Bus Transceiver
Input Bias Current (max)
40 uA
Maximum Power Dissipation
500 mW
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Polarity
Non-Inverting
Number Of Circuits
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-3012-2
935273595115
1. General description
2. Features
The 74LVC245A; 74LVCH245A are 8-bit transceivers featuring non-inverting 3-state bus
compatible outputs in both send and receive directions. The device features an output
enable (OE) input for easy cascading and a send/receive (DIR) input for direction control.
OE controls the outputs so that the buses are effectively isolated.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices in mixed
3.3 V and 5 V applications.
The 74LVCH245A bus hold on data inputs eliminates the need for external pull-up
resistors to hold unused inputs.
I
I
I
I
I
I
I
I
I
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74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
Rev. 05 — 25 August 2009
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
High-impedance when V
Bushold on all data inputs (74LVCH245A only)
Complies with JEDEC standard no. 8-1A
ESD protection:
Specified from 40 C to +85 C and 40 C to +125 C
N
N
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CC
= 0 V
Product data sheet

Related parts for 74LVC245ABQ,115

74LVC245ABQ,115 Summary of contents

Page 1

Octal bus transceiver; 3-state Rev. 05 — 25 August 2009 1. General description The 74LVC245A; 74LVCH245A are 8-bit transceivers featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The device features an output enable (OE) ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74LVC245AD +125 C 74LVCH245AD 74LVC245ADB +125 C 74LVCH245ADB 74LVC245APW +125 C 74LVCH245APW 74LVC245ABQ +125 C 74LVCH245ABQ 74LVC245ABX +125 C 74LVCH245ABX 4. Functional diagram DIR Fig 1. Logic diagram 74LVC_LVCH245A_5 Product data sheet 74LVC245A; 74LVCH245A Description SO20 plastic small outline package ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning 74LVC245A 74LVCH245A DIR GND Fig 3. Pin configuration for SO20 and (T)SSOP20 5.2 Pin description Table 2. Pin description Symbol Pin DIR GND 18, 17, 16, 15, 14, 13, 12 74LVC_LVCH245A_5 Product data sheet 74LVC245A; 74LVCH245A 001aak292 (1) The die substrate is attached to this pad using Fig 4 ...

Page 4

... NXP Semiconductors 6. Functional description [1] Table 3. Function selection Inputs OE DIR [ HIGH voltage level LOW voltage level don’t care high impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...

Page 5

... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). ...

Page 6

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions C input capacitance I C input/output I/O capacitance I bus hold LOW V BHL CC current I bus hold HIGH V BHH CC current I bus hold LOW V BHLO CC overdrive current I bus hold HIGH ...

Page 7

... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions C power per buffer dissipation capacitance [ the same as t and PLH PHL t is the same as t and PZL PZH t is the same as t and t ...

Page 8

... NXP Semiconductors OE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH See Table 8 for measurement points V and V are typical output voltage levels that occur with the output load Fig 6. Enable and disable times Table 8. Measurement points Supply voltage Input 1 2.7 V 2 ...

Page 9

... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 7. Test circuit for measuring switching times Table 9. Test data ...

Page 10

... NXP Semiconductors 12. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 11

... NXP Semiconductors SSOP20: plastic shrink small outline package; 20 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT339-1 Fig 9. ...

Page 12

... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 13

... NXP Semiconductors DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 14

... NXP Semiconductors DHXQFN20U: plastic dual in-line compatible thermal enhanced extremely thin quad flat package; no leads; 20 terminals; UTLP based; body 2.5 x 4.5 x 0.5 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.30 4.6 mm 0.5 0.00 0.18 4 ...

Page 15

... New SOT1045-1 package outline drawing (DHXQFN20U package). Product data sheet • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Added type number 74LVC245ABX and 74LVCH245ABX (DHXQFN20U package) Product specifi ...

Page 16

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 17

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 14 Revision history ...

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