TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 148

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.7.13
PK7 pins output “0”.
pins for an LCD controller (LCP0, LHSYNC, LLOAD, LFR, LVSYNC, and LGOE0 to
LGOE2).
Port K (PK0 to PK7)
PK0 to PK7 are 8-bit output ports. Resetting sets the output latch PK to “0”, and PK0 to
In addition to functioning as an output port function, port K also functions as output
The above settings are made using the function register PKFC.
Reset
Output latch
Function control
PKFC write
(on bit basis)
PK write
PK read
Figure 3.7.34 Port K0 to K7
LCP0, LLOAD, LFR, LVSYNC,
LHSYNC,LGOE0 to LGOE2
92CF26A-146
B
A
S
Output buffer
PK0 (LCP0)
PK1 (LLOAD)
PK2 (LFR)
PK3 (LVSYNC)
PK4 (LHSYNC)
PK5 (LGOE0)
PK6 (LGOE1)
PK7 (LGOE2)
TMP92CF26A
2009-06-25