TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 428

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TMP92xy26AXBG

Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy26AXBG

Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
(a-2) Receiving bulk mode
Below is the transaction format for receiving bulk transfer type.
Control flow
Below is the control-flow when the UDC receive an IN token.
UDC finishes normally.
This flow is shown in Figure 3.16.4.
1.
2. Condition of status register is confirmed.
3. Data packet is received.
4.
5. If CRC is compared with toggle and it finishes normally, ACK handshake is
Token: OUT
Data: DATA0/DATA1
Handshake: ACK, NAK, STALL
• INVALID condition: State returns to IDLE.
• STALL condition: When dataphase finishes, stall handshake is returned,
FIFO condition is confirmed, if data number of 1 packet is not prepared, present
transferred data is canceled, NAK handshake is returned after dataphase, and
the state returns to IDLE.
• Set transfer data number to DATASIZE register.
• Set DATASET register.
• Renew toggle bit, and prepare for next.
• Set STATUS to READY.
The token packet is received and the address endpoint number error is
confirmed, and it checks whether the relevant endpoint transfer mode
corresponds with the OUT token. If it does not correspond, the state returns to
IDLE.
Data is transferred from SIE of internal UDC to FIFO. At this point, it
confirms transferred data number and if there is more than the maximum
payload size of each endpoint, STATUS becomes to STALL and the state
returns to IDLE. ACK handshake does not return.
transferred CRC. If they do not correspond, STATUS is set to RX_ERR and the
state returns to IDLE. At this point ACK is not returned.
After retry, when next data is received normally, STATUS changes to DATIN.
If the data toggle does not correspond, it is judged not to have taken ACK in
the last loading the current loading is regarded as a retry of the last loading
and data is canceled. Set STATUS as RX_ERR, return to host and return to
IDLE. FIFO address pointer returns and the next data can be received.
returned.
Below is the process in the UDC.
After last data is transferred,
92CF26A-426
the state returns to IDLE, and data is canceled.
the counted CRC is compared with the
TMP92CF26A
2009-06-25

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