SAF-C161K-LM Infineon Technologies, SAF-C161K-LM Datasheet - Page 9

• Manufacturer Part Number: SAF-C161K-LM
• Manufacturer: Infineon Technologies

Specifications of SAF-C161K-LM

• Packages: PG-MQFP-80
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 1.0 KByte
• Program Memory: 0.0 KByte

Table 2
Symbol Pin
XTAL1
XTAL2
P3
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
P3.13
P4
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
Data Sheet
Num
2
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
23
24
Pin Definitions and Functions
Input
Outp.
I
O
IO
I
O
I
I
I
I
I/O
I/O
O
I/O
O
O
I/O
IO
O
O
O
O
O
O
Function
XTAL1:
XTAL2:
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.
Port 3 is a 12-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 3 outputs can be configured as push/
pull or open drain drivers. The Port 3 pins serve for following
alternate functions:
CAPIN
This alternate input is only available in the C161O.
T3OUT
T3EUD
T4IN
T3IN
T2IN
MRST
MTSR
TxD0
RxD0
BHE
WRH
SCLK
Port 4 is a 6-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 4 can be used to output the segment
address lines:
A16 Least Significant Segment Address Line
A17 Segment Address Line
A18 Segment Address Line
A19 Segment Address Line
A20 Segment Address Line
A21 Most Significant Segment Address Line
Input to the oscillator amplifier and input
to the internal clock generator
Output of the oscillator amplifier circuit.
GPT2 Register CAPREL Capture Input
GPT1 Timer T3 Toggle Latch Output
GPT1 Timer T3 External Up/Down Control Input
GPT1 Timer T4 Count/Gate/Reload/Capture Inp
GPT1 Timer T3 Count/Gate Input
GPT1 Timer T2 Count/Gate/Reload/Capture Inp
SSC Master-Receive/Slave-Transmit Inp./Outp.
SSC Master-Transmit/Slave-Receive Outp./Inp.
ASC0 Clock/Data Output (Async./Sync.)
ASC0 Data Input (Async.) or Inp./Outp. (Sync.)
External Memory High Byte Enable Signal,
External Memory High Byte Write Strobe
SSC Master Clock Output / Slave Clock Input
5
V2.0, 2001-01
C161O
C161K