74AHCT1G07GW,125 NXP Semiconductors, 74AHCT1G07GW,125 Datasheet

IC BUFF N-INV OP/DRAIN 5TSSOP

74AHCT1G07GW,125

Manufacturer Part Number
74AHCT1G07GW,125
Description
IC BUFF N-INV OP/DRAIN 5TSSOP
Manufacturer
NXP Semiconductors
Series
74AHCTr
Datasheet

Specifications of 74AHCT1G07GW,125

Package / Case
SC-70-5, SC-88A, SOT-323-5, SOT-353, 5-TSSOP
Logic Type
Buffer/Line Driver, Non-Inverting with Open Drain
Number Of Elements
1
Number Of Bits Per Element
1
Current - Output High, Low
8mA, 8mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
AHCT
Number Of Channels Per Chip
1
Polarity
Non-Inverting
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Low Level Output Current
8 mA
Maximum Power Dissipation
250 mW
Minimum Operating Temperature
- 40 C
Output Current
25 mA
Output Type
Open Drain
Output Voltage
7 V
Number Of Lines (input / Output)
1 / 1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74AHCT1G07GW-G
74AHCT1G07GW-G
935267471125
1. General description
2. Features
3. Ordering information
Table 1.
Type number
74AHC1G07GW
74AHCT1G07GW
74AHC1G07GV
74AHCT1G07GV
Ordering information
Package
Temperature range
74AHC1G07 and 74AHCT1G07 are high-speed Si-gate CMOS devices. They provide a
non-inverting buffer.
The output of these devices is open-drain and can be connected to other open-drain
outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. For
digital operation this device must have a pull-up resistor to establish a logic HIGH-level.
The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.
The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.
I
I
I
I
I
40 C to +125 C
40 C to +125 C
74AHC1G07; 74AHCT1G07
Buffer with open-drain output
Rev. 06 — 7 June 2007
High noise immunity
Low power dissipation
SOT353-1 and SOT753 package options
ESD protection:
Specified from 40 C to +125 C
N
N
N
HBM JESD22-A114E: exceeds 2000 V
MM JESD22-A115-A: exceeds 200 V
CDM JESD22-C101C: exceeds 1000 V
Name
TSSOP5
SC-74A
Description
plastic thin shrink small outline package;
5 leads; body width 1.25 mm
plastic surface-mounted package; 5 leads
Product data sheet
Version
SOT353-1
SOT753

Related parts for 74AHCT1G07GW,125

74AHCT1G07GW,125 Summary of contents

Page 1

Buffer with open-drain output Rev. 06 — 7 June 2007 1. General description 74AHC1G07 and 74AHCT1G07 are high-speed Si-gate CMOS devices. They provide a non-inverting buffer. The output of these devices is open-drain and can be connected to ...

Page 2

... NXP Semiconductors 4. Marking Table 2. Marking codes Type number 74AHC1G07GW 74AHC1G07GV 74AHCT1G07GW 74AHCT1G07GV 5. Functional diagram mna589 Fig 1. Logic symbol 6. Pinning information 6.1 Pinning Fig 4. Pin configuration 6.2 Pin description Table 3. Pin description Symbol Pin n. GND 74AHC_AHCT1G07_6 Product data sheet 74AHC1G07; 74AHCT1G07 ...

Page 3

... NXP Semiconductors 7. Functional description Table 4. Function table H = HIGH voltage level LOW voltage level high-impedance OFF-state Input Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input voltage I I input clamping current ...

Page 4

... NXP Semiconductors 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions For type 74AHC1G07 V HIGH-level input voltage LOW-level input voltage LOW-level output voltage 4.0 mA 8.0 mA input leakage GND current 5 OFF-state output current GND ...

Page 5

... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics GND = 3.0 ns. For test circuit see r f Symbol Parameter Conditions For type 74AHC1G07 t OFF-state see PZL to LOW V CC propagation C delay LOW see PLZ OFF-state V CC propagation C delay power per buffer; PD dissipation pF MHz; L capacitance V = GND to V ...

Page 6

... NXP Semiconductors 12. Waveforms A input Y output Measurement points are given in Fig 5. Input (A) to output (Y) propagation delays Table 9. Measurement point Type Input V I 74AHC1G07 GND to V 74AHCT1G07 GND to 3.0 V GENERATOR Test data is given in Table 8. Definitions for test circuit Load capacitance including jig and probe capacitance. ...

Page 7

... NXP Semiconductors 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1. DIMENSIONS (mm are the original dimensions UNIT max. 0.1 1.0 mm 1.1 0.15 0 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION IEC SOT353-1 Fig 7 ...

Page 8

... NXP Semiconductors Plastic surface-mounted package; 5 leads DIMENSIONS (mm are the original dimensions UNIT 0.100 0.40 1.1 0.26 mm 0.013 0.25 0.9 0.10 OUTLINE VERSION IEC SOT753 Fig 8. Package outline SOT753 (SC-74A) 74AHC_AHCT1G07_6 Product data sheet 74AHC1G07; 74AHCT1G07 scale 3.1 1.7 3.0 0.6 0.95 2 ...

Page 9

... Release date 74AHC_AHCT1G07_6 20070607 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Package SOT353 changed to SOT353-1 in • ...

Page 10

... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...

Page 11

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 14 Abbreviations ...

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