74LVT126PW,118 NXP Semiconductors, 74LVT126PW,118 Datasheet

IC BUFF TRI-ST QD N-INV 14TSSOP

74LVT126PW,118

Manufacturer Part Number
74LVT126PW,118
Description
IC BUFF TRI-ST QD N-INV 14TSSOP
Manufacturer
NXP Semiconductors
Series
74LVTr
Datasheet
1.74LVT126D112.pdf (15 pages)

Specifications of 74LVT126PW,118

Package / Case
14-TSSOP
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
1
Current - Output High, Low
32mA, 64mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Logic Family
LVT
Number Of Channels Per Chip
4
Polarity
Non-Inverting
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
High Level Output Current
- 32 mA
Input Bias Current (max)
7000 uA
Low Level Output Current
64 mA
Minimum Operating Temperature
- 40 C
Output Type
3-State
Propagation Delay Time
2.4 ns (Typ) @ 3.3 V
Number Of Lines (input / Output)
4 / 4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-4628-2
74LVT126PW-T
74LVT126PW-T
935209470118
1. General description
2. Features
3. Quick reference data
The LVT126 is a high-performance BiCMOS product designed for V
This device combines low static and dynamic power dissipation with high speed and high
output drive. The 74LVT126 device is a quad buffer that is ideal for driving bus lines. The
device features four output enable inputs (1OE, 2OE, 3OE and 4OE), each controlling one
of the 3-state outputs.
Table 1:
GND = 0 V; T
Symbol Parameter
t
t
C
C
I
PLH
PHL
CC
I
O
74LVT126
3.3 V quad buffer; 3-state
Rev. 04 — 11 February 2005
Quad bus interface
3-state buffers
Output capability: +64 mA and 32 mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
Live insertion and extraction permitted
No bus current loading when output is tied to 5 V bus
Power-up 3-state
Latch-up protection:
ESD protection:
JESD78: exceeds 500 mA
MIL STD 883 method 3015: exceeds 2000 V
Machine model: exceeds 200 V
propagation delay nA to nY C
propagation delay nA to nY C
input capacitance
output capacitance
quiescent supply current
Quick reference data
amb
= 25 C.
Conditions
V
outputs disabled;
V
outputs disabled;
V
I
O
CC
L
L
= 0 V or V
= 50 pF; V
= 50 pF; V
= 0 V or 3.0 V
= 3.6 V
CC
CC
CC
= 3.3 V
= 3.3 V
Product data sheet
Min
-
-
-
-
-
CC
Typ
2.3
2.4
4
8
0.13
operation at 3.3 V.
Max
-
-
-
-
-
Unit
ns
ns
pF
pF
mA

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74LVT126PW,118 Summary of contents

Page 1

V quad buffer; 3-state Rev. 04 — 11 February 2005 1. General description The LVT126 is a high-performance BiCMOS product designed for V This device combines low static and dynamic power dissipation with high speed and high output ...

Page 2

Philips Semiconductors 4. Ordering information Table 2: Ordering information Type number Package Temperature range Name 74LVT126D +85 C 74LVT126DB +85 C 74LVT126PW +85 C 74LVT126BQ + ...

Page 3

Philips Semiconductors 6. Pinning information 6.1 Pinning Fig 3. Pin configuration SO14, SSOP14 6.2 Pin description Table 3: Symbol 1OE 1A 1Y 2OE 2A 2Y GND 3Y 3A 3OE 4Y 4A 4OE V CC 9397 750 14553 Product data sheet ...

Page 4

Philips Semiconductors 7. Functional description 7.1 Function table Table 4: Input nOE [ HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. 8. Limiting values Table 5: In ...

Page 5

Philips Semiconductors 9. Recommended operating conditions Table 6: Symbol amb 10. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to ...

Page 6

Philips Semiconductors Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I external current into output output in HIGH-state when power-up or power-down PU PD 3-state ...

Page 7

Philips Semiconductors Table 8: Dynamic characteristics GND = 2 Symbol Parameter t output disable time nOE to nY PHZ t output disable time nOE to ...

Page 8

Philips Semiconductors a. Input pulse definition b. Test circuit Fig 7. Load circuitry for switching times Table 9: Input V I 2.7 V 9397 750 14553 Product data sheet negative V M pulse ...

Page 9

Philips Semiconductors 13. Package outline SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT ...

Page 10

Philips Semiconductors SSOP14: plastic shrink small outline package; 14 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1.80 mm ...

Page 11

Philips Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 ...

Page 12

Philips Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area ...

Page 13

Philips Semiconductors 14. Revision history Table 10: Revision history Document ID Release date 74LVT126_4 20050211 • Modifications: The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. • Figure ...

Page 14

Philips Semiconductors 15. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...

Page 15

Philips Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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