74LVC3G17DP,125 NXP Semiconductors, 74LVC3G17DP,125 Datasheet

IC BUFF SCHMT TRG TRPL 8TSSOP

74LVC3G17DP,125

Manufacturer Part Number
74LVC3G17DP,125
Description
IC BUFF SCHMT TRG TRPL 8TSSOP
Manufacturer
NXP Semiconductors
Series
74LVCr
Datasheet

Specifications of 74LVC3G17DP,125

Logic Type
Schmitt Trigger - Buffer, Driver
Package / Case
8-TSSOP
Number Of Elements
3
Number Of Bits Per Element
1
Current - Output High, Low
32mA, 32mA
Voltage - Supply
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
74LVC
Number Of Channels Per Chip
3
Polarity
Non-Inverting
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.65 V
Maximum Operating Temperature
125 C
Mounting Style
SMD/SMT
High Level Output Current
- 32 mA
Input Bias Current (max)
40 uA
Low Level Output Current
32 mA
Minimum Operating Temperature
-40 C
Propagation Delay Time
5.4 ns
Number Of Lines (input / Output)
3 / 3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74LVC3G17DP-G
74LVC3G17DP-G
935275564125
1. General description
2. Features and benefits
3. Applications
The 74LVC3G17 provides three non-inverting buffers with Schmitt trigger action. It is
capable of transforming slowly changing input signals into sharply defined, jitter-free
output signals.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the
74LVC3G17 as a translator in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
74LVC3G17
Triple non-inverting Schmitt trigger with 5 V tolerant input
Rev. 7 — 4 November 2010
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
ESD protection:
±24 mA output drive (V
CMOS low-power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C
Wave and pulse shapers for highly noisy environments
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CC
= 3.0 V)
Product data sheet
OFF
. The I
OFF

Related parts for 74LVC3G17DP,125

74LVC3G17DP,125 Summary of contents

Page 1

Triple non-inverting Schmitt trigger with 5 V tolerant input Rev. 7 — 4 November 2010 1. General description The 74LVC3G17 provides three non-inverting buffers with Schmitt trigger action capable of transforming slowly changing input signals into sharply ...

Page 2

... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +125 °C 74LVC3G17DP −40 °C to +125 °C 74LVC3G17DC −40 °C to +125 °C 74LVC3G17GT −40 °C to +125 °C 74LVC3G17GF −40 °C to +125 °C 74LVC3G17GD −40 °C to +125 °C 74LVC3G17GM − ...

Page 3

... NXP Semiconductors 6. Functional diagram 001aah860 Fig 1. Logic symbol Fig 3. Logic diagram (one gate) 7. Pinning information 7.1 Pinning 74LVC3G17 GND 4 001aab106 Fig 4. Pin configuration SOT505-2 and SOT765-1 74LVC3G17 Product data sheet Triple non-inverting Schmitt trigger with 5 V tolerant input Fig Fig 5. All information provided in this document is subject to legal disclaimers. ...

Page 4

... NXP Semiconductors 74LVC3G17 GND 4 Transparent top view Fig 6. Pin configuration SOT996-2 7.2 Pin description Table 3. Pin description Symbol Pin SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT996-2, SOT1116 and SOT1203 1A, 2A GND 4 1Y, 2Y Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level. ...

Page 5

... NXP Semiconductors 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage O I output current ...

Page 6

... NXP Semiconductors 11. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = −40 °C to +85 °C T amb V LOW-level output voltage OL V HIGH-level output voltage OH I input leakage current I I power-off leakage current OFF I supply current CC Δ ...

Page 7

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I power-off leakage current OFF I supply current CC ΔI additional supply current CC [1] All typical values are measured at T [2] These typical values are measured at V 12. Dynamic characteristics Table 8 ...

Page 8

... NXP Semiconductors 13. Waveforms Measurement points are given in V and V are typical output voltage drops that occur with the output load Fig 8. The input (nA) to output (nY) propagation delays and the output transition times Table 9. Measurement points Supply voltage 1. ...

Page 9

... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 9. Test circuit for measuring switching times Table 10. ...

Page 10

... NXP Semiconductors 14. Transfer characteristics Table 11. Transfer characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V positive-going see T+ threshold voltage negative-going see T− threshold voltage hysteresis voltage ( Figure [1] All typical values are measured at T 15. Waveforms transfer characteristics T− ...

Page 11

... NXP Semiconductors Fig 12. Typical transfer characteristic (1) Positive-going edge. (2) Negative-going edge. Linear change of V between 0 2.0 V. All values given are typical unless otherwise specified. I Fig 13. Average function 74LVC3G17 Product data sheet Triple non-inverting Schmitt trigger with 5 V tolerant input (mA 0 (mA) ...

Page 12

... NXP Semiconductors 16. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.00 0.75 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...

Page 13

... NXP Semiconductors VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 14

... NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. 8× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 2.0 mm 0.5 0.04 0.17 1.9 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...

Page 15

... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1. 0.5 mm terminal 1 index area (2) (4× terminal 1 index area Dimensions (1) Unit max 0.5 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 16

... NXP Semiconductors XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 0.5 mm terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.35 2.1 mm 0.5 0.00 0.15 1.9 OUTLINE VERSION IEC SOT996 Fig 18. Package outline SOT996-2 (XSON8U) ...

Page 17

... NXP Semiconductors XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.65 mm 0.5 0.00 ...

Page 18

... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.25 mm nom 0.15 1.20 min 0.12 1.15 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 19

... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 20

... NXP Semiconductors 17. Abbreviations Table 12. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 18. Revision history Table 13. Revision history Document ID Release date 74LVC3G17 v.7 20101104 • Modifications: Added type number 74LVC3G17GF (SOT1089 / XSON8 package). ...

Page 21

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 22

... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 20. Contact information For more information, please visit: For sales office addresses, please send an email to: 74LVC3G17 Product data sheet Triple non-inverting Schmitt trigger with 5 V tolerant input 19 ...

Page 23

... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Functional description . . . . . . . . . . . . . . . . . . . 4 9 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 13 Waveforms ...

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