74LVC544AD,112 NXP Semiconductors, 74LVC544AD,112 Datasheet

IC TRANSCEIVER 8BIT INV 24SOIC

74LVC544AD,112

Manufacturer Part Number
74LVC544AD,112
Description
IC TRANSCEIVER 8BIT INV 24SOIC
Manufacturer
NXP Semiconductors
Series
74LVCr
Datasheet
1.74LVC544APW118.pdf (20 pages)

Specifications of 74LVC544AD,112

Logic Type
Transceiver, Inverting
Number Of Elements
1
Number Of Bits Per Element
8
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
24-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74LVC544AD
74LVC544AD
935250540112
1. General description
2. Features
The 74LVC544A is a high-performance, low-power, low-voltage, Si-gate CMOS device
superior to most advanced CMOS compatible TTL families.
The 74LVC544A is an octal registered inverting transceiver containing two sets of D-type
latches for temporary storage of the data flow in either direction. Separate latch enable
inputs (LEAB and LEBA) and output enable inputs (OEAB and OEBA) are provided for
each register to permit independent control of inputting and outputting in either direction of
the data flow.
The 74LVC544A contains eight D-type latches, with separate inputs and controls for each
set. For data flow from pins A to B, for example, the A to B enable input (pin EAB) must be
LOW in order to enter data from pins A0 to A7 or take data from pins B0 to B7. With
pin EAB LOW, a LOW signal on the A to B latch enable input (pin LEAB) makes the A to B
latches transparent; a subsequent LOW-to-HIGH transition on pin LEAB puts the A data
into the latches where it is stored and the B outputs no longer change with the A inputs.
With pins EAB and OEAB both LOW, the 3-state B output buffers are active and display
the data present at the outputs of the A latches.
74LVC544A
Octal D-type registered transceiver; inverting; 3-state
Rev. 03 — 11 May 2004
5 V tolerant inputs/outputs for interfacing with 5 V logic
Supply voltage range from 1.2 V to 3.6 V
Complies with JEDEC standard JESD8-B/JESD36
CMOS low-power consumption
Direct interface with TTL levels
8-bit octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
Supports partial power-down applications; inputs/outputs are high-impedance when
V
ESD protection:
Specified from 40 C to +85 C and 40 C to +125 C.
CC
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
= 0 V
Product data sheet

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74LVC544AD,112 Summary of contents

Page 1

Octal D-type registered transceiver; inverting; 3-state Rev. 03 — 11 May 2004 1. General description The 74LVC544A is a high-performance, low-power, low-voltage, Si-gate CMOS device superior to most advanced CMOS compatible TTL families. The 74LVC544A is an octal registered ...

Page 2

Philips Semiconductors 3. Quick reference data Table 1: GND = Symbol PHL PLH I [ input frequency in MHz ...

Page 3

Philips Semiconductors 5. Functional diagram OEBA 13 OEAB EAB 11 23 EBA 14 LEAB LEBA 1 Fig 1. Logic symbol. 9397 750 13127 ...

Page 4

Philips Semiconductors OEBA EBA LEBA OEAB EAB LEAB An Fig 3. Logic diagram. 6. Pinning information 6.1 Pinning Fig 4. Pin configuration for SO24 and (T)SSOP24. 9397 750 13127 Product data sheet Octal D-type registered transceiver; inverting; 3-state LE D ...

Page 5

Philips Semiconductors 6.2 Pin description Table 3: Pin Functional description 7.1 Function table Table 4: ...

Page 6

Philips Semiconductors Table 4: Operating mode Transparent Hold (do nothing) [ for direction and BA for direction HIGH voltage level LOW voltage level HIGH state ...

Page 7

Philips Semiconductors Table 6: Symbol Parameter amb 10. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter [ ...

Page 8

Philips Semiconductors Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current LI I 3-state output OFF-state ...

Page 9

Philips Semiconductors Table 8: Dynamic characteristics GND = 0 V; see Figure 9 for test circuit. Symbol Parameter 3-state output enable time OEBA to An; PZH PZL OEAB to Bn 3-state output enable time EBA to An; ...

Page 10

Philips Semiconductors Table 8: Dynamic characteristics GND = 0 V; see Figure 9 for test circuit. Symbol Parameter +125 C amb propagation delay A PHL PLH n propagation delay ...

Page 11

Philips Semiconductors [3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [ used to determine the dynamic power dissipation ( ...

Page 12

Philips Semiconductors Fig 6. Latch enable input (LEXX) pulse width and latch enable input to output (An, Bn) Fig 7. Data set-up and hold times for the inputs (An, Bn) to LEXX and EXX inputs. 9397 750 13127 Product data ...

Page 13

Philips Semiconductors Fig 8. 3-state enable and disable times. Table 10: Supply voltage V CC 1.2 V 2 3.6 V 9397 750 13127 Product data sheet Octal D-type registered transceiver; inverting; 3-state V I OEXX, EXX ...

Page 14

Philips Semiconductors Fig 9. Load circuitry for switching times. Table 11: Supply voltage V CC 1.2 V 2 3.6 V [1] The circuit performs better when R 9397 750 13127 Product data sheet Octal D-type registered ...

Page 15

Philips Semiconductors 13. Package outline SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT ...

Page 16

Philips Semiconductors SSOP24: plastic shrink small outline package; 24 leads; body width 5 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. ...

Page 17

Philips Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm ...

Page 18

Philips Semiconductors 14. Revision history Table 12: Revision history Document ID Release date 74LVC544A_3 20040511 • Modifications: The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors • Table ...

Page 19

Philips Semiconductors 15. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...

Page 20

Philips Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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