CS61574A/75 Cirrus Logic, Inc., CS61574A/75 Datasheet
CS61574A/75
Related parts for CS61574A/75
CS61574A/75 Summary of contents
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Features Provides Analog Transmission Line Interface for T1 and E1 Applications Provides Line Driver, Jitter Attenuator and Clock Recovery Functions Fully Compliant with AT&T 62411 Stratum 4 Jitter Requirements Low Power Consumption (typically 175 mW) B8ZS/HDB3/AMI Encoder/Decoder ...
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ABSOLUTE MAXIMUM RATINGS Parameter DC Supply (referenced to RGND, TGND=0V) Input Voltage, Any Pin Input Current, Any Pin Ambient Operating Temperature Storage Temperature WARNING:Operations at or beyond these limits may result in permanent damage to the device. Normal operation is ...
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ANALOG SPECIFICATIONS Parameter Transmitter AMI Output Pulse Amplitudes E1, 75 E1, 120 T1, FCC Part 68 T1, DSX-1 E1 Zero (space) level (LEN2/1/0 = 0/0/0) 1:1 transformer and 75 1:1.26 transformer and 120 Recommended Output Load at TTIP and TRING ...
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ANALOG SPECIFICATIONS Parameter Receiver RTIP/RRING Input Impedance Sensitivity Below DSX (0dB = 2.4V) Data Decision Threshold T1, DSX-1 T1, DSX-1 T1, FCC Part 68 and E1 Allowable Consecutive Zeros before LOS Receiver Input Jitter Tolerance 10kHz - 100kHz 2kHz 10Hz ...
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ANALOG SPECIFICATIONS Parameter Jitter Attenuator Jitter Attenuation Curve Corner Frequency CS61574A CS61575 CS61574A T1 Receiver Jitter Transfer Jitter Freq. [Hz] 10 100 500 1k 10k, 40k CS61575 T1 Receiver Jitter Transfer Jitter Freq. [Hz] 10 100 500 1k 10k, 40k ...
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T1 SWITCHING CHARACTERISTICS GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3) Parameter Crystal Frequency TCLK Frequency TCLK Pulse Width ACLKI Duty Cycle ACLKI Frequency RCLK Duty Cycle Rise Time, All ...
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SWITCHING CHARACTERISTICS Inputs: Logic 0 = 0V, Logic 1 = RV+) Parameter SDI to SCLK Setup Time SCLK to SDI Hold Time SCLK Low Time SCLK High Time SCLK Rise and Fall Time CS to SCLK Setup Time SCLK to ...
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TCLK t su2 TPOS/TNEG Figure 3a. Transmit Clock and Data Switching Characteristics SCLK t cdh t dc SDI LSB CONTROL CS SCLK t cdv SDO CLKE = 1 LEN0/1/2, TAOS, RLOOP, LLOOP, RCODE, ...
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THEORY OF OPERATION Enhancements in CS61575 and CS61574A The CS61574A and CS61575 provide higher per- formance and more features than the CS61574 including: AT&T 62411, Stratum 4 compliant jitter at- tenuation over the full range of operating frequency and jitter ...
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TPOS TNEG CS62180B FRAMER CIRCUIT RPOS RNEG TCODE TDATA REPEATER OR CODER MUX RDATA BPV AIS P SERIAL PORT 5 CONTROL TPOS TNEG CS62180B FRAMER CIRCUIT RPOS RNEG 10 HARDWARE MODE TAOS LLOOP RLOOP LEN0/1/2 CONTROL LINE ...
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EXTENDED FUNCTION PIN HARDWARE HARDWARE 3 TPOS TRANSMITTER 4 TNEG 6 RNEG 7 RPOS RECEIVER/DPM 11 DPM 17 MTIP 18 MRING LEN0 24 LEN1 CONTROL 25 LEN2 26 RLOOP 27 LLOOP 28 TAOS Table 2. Pin Definitions ...
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Percent of nominal peak 269 ns voltage 120 110 244 ns 100 194 -10 -20 219 ns 488 ns Figure 9. Mask of the Pulse at the 2048 kbps Interface The E1 G.703 pulse ...
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RTIP RRING A block diagram of the receiver is shown in Fig- ure 10. The two leads of the transformer (RTIP and RRING) have opposite polarity allowing the receiver to treat RTIP and RRING as unipolar sig- ...
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In the Hardware Mode, data at RPOS and RNEG should be sampled on the rising edge of RCLK, the recovered clock. In the Extended Hardware Mode, data at RDATA should be sampled on the falling edge of RCLK. In the ...
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Minimum Attenuation Limit 10 62411 Requirements Maximum Attenuation Limit 50 Measured Performance 100 Frequency in Hz Figure 12. Typical Jitter Transfer Function The FIFO in the jitter attenuator is designed to ...
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Remote Loopback Remote loopback is selected by taking RLOOP, pin 26, high or by setting the RLOOP register bit via the serial interface. In remote loopback, the recovered clock and data input on RTIP and RRING are sent through the ...
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Alarm Indication Signal In the Extended Hardware Mode, the receiver sets the output pin AIS high when less than 9 zeros are detected out of 8192 bit periods. AIS returns low when 9 or more zeros are detected out of ...
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CS SCLK SDI R Address/Command Byte SDO An address/command byte, shown in Table 9, pre- cedes a data register. The first bit of the address/command byte determines whether a read or a write is requested. The next six ...
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Bits Status Reset has occurred or no program input TAOS in effect LLOOP in effect TAOS/LLOOP in effect RLOOP in effect. 1 ...
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PIN DESCRIPTIONS ACLKI TCLK TPOS TNEG MODE RNEG RPOS RCLK XTALIN XTALOUT TGND 20 Hardware Mode ACLKI TAOS 1 28 TCLK LLOOP 2 27 TPOS RLOOP 26 3 TNEG LEN2 4 25 MODE LEN1 5 24 RNEG LEN0 6 23 ...
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ACLKI TCLK TDATA TCODE MODE RDATA RCLK XTALIN XTALOUT TGND DS154F2 Extended Hardware Mode ACLKI TAOS 1 28 TCLK LLOOP 2 27 TDATA RLOOP 26 3 TCODE LEN2 4 25 MODE LEN1 5 24 BPV LEN0 6 23 RDATA RGND ...
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ACLKI TCLK TPOS TNEG MODE RNEG RPOS RCLK XTALIN XTALOUT TGND 22 Host Mode ACLKI CLKE 1 28 TCLK SCLK 2 27 TPOS TNEG SDO 4 25 MODE SDI 5 24 RNEG INT 6 23 RPOS RGND ...
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Power Supplies RGND - Ground, Pin 22. Power supply ground for all subcircuits except the transmit driver; typically 0 Volts. RV+ - Power Supply, Pin 21. Power supply for all subcircuits except the transmit driver; typically +5 Volts. TGND - ...
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LEN0, LEN1, LEN2 - Line Length Selection, Pins 23, 24 and 25. (Hardware and Extended Hardware Modes) Determines the shape and amplitude of the transmitted pulse to accommodate several cable types and lengths. See Table 3 for information on line ...
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TAOS - Transmit All Ones Select, Pin 28. (Hardware and Extended Hardware Modes) Setting TAOS to a logic 1 causes continuous ones to be transmitted at the frequency determined by TCLK. TCODE - Transmitter Encoder Select, Pin 4. (Extended Hardware ...
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TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13 and 16. The AMI signal is driven to the line through these pins. The transmitter output is designed to drive a 75 load between TTIP and TRING. A transformer is required ...
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D SEATING PLANE e1 B1 NOTES: 1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN 0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED ...
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APPLICATIONS + 28 Control & 12 Monitor 11 RV+ Frame Format Encoder/ Decoder XTL 10 Frequency MHz 1.544 (T1) 2.048 (E1) Line Interface Figures A1-A3 show typical T1 and E1 line inter- face application circuits. Table A1 shows the external ...
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Control & Monitor Frame Format Encoder/ Decoder XTL Figure A2. 120 + Control & Monitor Frame Format Encoder/ Decoder XTL Figure A3. 75 DS154F2 + 0.1 F 1.0 F RGND TGND 21 15 RV+ TV+ 28 ...
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Parameter Turns Ratio Primary Inductance Primary Leakage Inductance Secondary Leakage Inductance Interwinding Capacitance ET-constant Transformers Recommended transmitter and receiver trans- former specifications are shown in Table A2. The transformers in Table A3 have been tested and recommended for use with ...
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Application Turns Ratio(s) RX: 1:2CT T1 & E1 TX: 1:1.15 T1 TX: 1:1.26 1:1 E1 (75 & 120 RX &TX: 1:2CT T1 1:1.15 RX &TX: 1:2CT 1:1.26 E1 (75 & 120 1:1 RX &TX: 1:2CT T1 1:1.15 RX &TX: 1:2CT ...
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Notes • ...
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Line Interface Evaluation Board Features Socketed Line Interface Device All Required Components for Complete Line Interface Evaluation Configuration by DIP Switch or Serial Interface LED Status Indicators for Alarm Conditions Support for Host, Hardware, and Extended Hardware Modes Mode Select ...
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POWER SUPPLY As shown on the evaluation board schematic in Figure 1, power is supplied to the evaluation board from an external +5 Volt supply connected to the two binding posts labeled +5V and GND. Transient suppressor D10 protects the ...
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GND (0V) RNEG (BPV) RCLK TCLK TPOS (TDATA) RPOS (RDATA) R1 51.1 RV+ ACLKI R15 TNEG 100 S2 RCODE TCODE LEN0/INT LEN1/SDI LEN2/SD0 RLOOP/CS LLOOP/SCLK TAOS/CLKE INT SDI SDO CS SCLK D8 D9 JP1 1N914 S1 RESET R4 221k ...
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Performance Monitor alarm. The LED labeled LOS illuminates when the line interface receiver has detected a loss of signal. Extended Hardware Mode In the Extended Hardware operating mode, the line interface is configured using DIP switch S2. The digital control ...
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The evaluation board supports 100 T1, 75 coax E1, and 120 eration. The CDB61534, CDB61535, CDB6158, CDB61574, and CDB61577 are supplied from the factory with a 1:2 transmit transformer that may be used for all T1 and E1 applications. The ...
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A letter at the intersection of a row and column in Table 2 indicates that the selected transformer is supported for use with the device. The transformer is installed in the evaluation board with pin 1 positioned to match ...
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TRANSFORMER 1,2 (Turns Ratio) PE-65351 (1:2CT) Schott 12930 (1:2CT) PE-65388 (1:1.15) Schott 12931 (1:1.15) PE-65389 (1:1:1.26) Schott 12932 (1:1:1.26) PE-64951 (dual 1:2CT) Schott 11509 (dual 1:2CT) PE-65565 (dual 1:1.15 & 1:2CT) Schott 12531 (dual 1:1.15 & 1:2CT) PE-65566 (dual 1:1:1.26 ...
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Figure 2. Silk Screen Layer (NOT TO SCALE) LINE INTERFACE EVALUATION BOARD DS40DB3 ...
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Figure 3. Top Ground Plane Layer (NOT TO SCALE) DS40DB3 LINE INTERFACE EVALUATION BOARD 41 ...
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Figure 4. Bottom Trace Layer (NOT TO SCALE) 42 LINE INTERFACE EVALUATION BOARD DS40DB3 ...
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Notes • ...
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TM Smart Analog is a Trademark of Crystal Semiconductor Corporation ...