CS61574A/75 Cirrus Logic, Inc., CS61574A/75 Datasheet - Page 18

• Manufacturer Part Number: CS61574A/75
• Description: T1/E1 Line Interface Unit for Stratum-4 applications
• Manufacturer: Cirrus Logic, Inc.

SDO
An address/command byte, shown in Table 9, pre-
cedes a data register. The first bit of the
address/command byte determines whether a read
or a write is requested. The next six bits contain
the address. The line interface responds to address
16 (0010000). The last bit is ignored.
The data register, shown in Table 10, can be writ-
ten to the serial port. Data is input on the eight
clock cycles immediately following the ad-
dress/command byte. Bits 0 and 1 are used to
clear an interrupt issued from the INT pin, which
occurs in response to a loss of signal or a problem
with the output driver.
18
CS
SCLK
SDI
MSB, last bit
MSB, last bit
LSB, first bit
LSB, first bit
in
in
Table 9. Address/Command Byte
Table 10. Input Data Register
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
R/W
clr DPM Clear Driver Performance
RLOOP Remote Loopback
clr LOS Clear Loss Of Signal
LLOOP Local Loopback
ADDP LSB of address, Must be 0
ADD1 Must be 0
ADD2 Must be 0
ADD3 Must be 0
ADD4 Must be 1
LEN0
LEN1
LEN2
TAOS
R/W
X
-
0
Read/Write Select; 0 = write, 1 = read
Reserved - Must be 0
Don’t Care
Bit 0 - Line Length Select
Bit 1 - Line Length Select
Bit 2 - Line Length Select
Transmit All Ones Select
Address/Command Byte
0
0
Figure 13. Input/Output Timing
0
1
0
Writing a "1" to either "Clear LOS" or "Clear
DPM" over the serial interface has three effects:
Writing a "0" to either "Clear LOS" or "Clear
DPM" enables the corresponding interrupt for
LOS or DPM.
Output data from the serial interface is presented
as shown in Tables 11 and 12. Bits 2, 3 and 4 can
be read to verify line length selection. Bits 5, 6
and 7 must be decoded. Codes 101, 110 and 111
(Bits 5, 6 and 7) indicate intermittent loss of sig-
nal and/or driver problems.
SDO goes to a high impedance state when not in
use. SDO and SDI may be tied together in appli-
cations where the host processor has a
bi-directional I/O port.
0
LSB, first bit
1) The current interrupt on the serial interface
2) Output data bits 5, 6 and 7 will be reset as
3) Future interrupts for the corresponding LOS
D0
D0
will be cleared. (Note that simply reading
the register bits will not clear the inter-
rupt).
appropriate.
or DPM will be prevented from occurring.
in
Table 11. Output Data Bits 0 - 4
D1
D1
0
1
2
3
4
LEN0
LEN1
LEN2
DPM
LOS
D2
D2
Data Input/Output
Loss Of Signal
Driver Performance
Bit 0 - Line Length Select
Bit 1 - Line Length Select
Bit 2 - Line Length Select
D3
D3
CS61574A CS61575
D4
D4
D5
D5
D6
D6
DS154F2
D7
D7