CS61574A-75 Cirrus Logic, Inc., CS61574A-75 Datasheet - Page 12

• Manufacturer Part Number: CS61574A-75
• Description: T1-E1 Line Interface Unit for Stratum-4 applications
• Manufacturer: Cirrus Logic, Inc.

The E1 G.703 pulse shape is supported with line
length selection LEN2/1/0=0/0/0. The pulse
width will meet the G.703 pulse shape template
shown in Figure 9, and specified in Table 4.
The CS61574A and CS61575 will detect a static
TCLK, and will force TTIP and TRING low to
prevent transmission when data is not present.
When any transmit control pin (TAOS, LEN0-2
or LLOOP) is toggled, the transmitter outputs
will require approximately 22 bit periods to stabi-
lize. The transmitter will take longer to stabilize
12
Figure 9. Mask of the Pulse at the 2048 kbps Interface
120
110
100
-10
-20
90
80
50
10
0
Percent of
nominal
peak
voltage
Nominal peak voltage of a mark (pulse)
Peak voltage of a space (no pulse)
Nominal pulse width
Ratio of the amplitudes of positive and negative
pulses at the center of the pulse interval
Ratio of the widths of positive and negative
pulses at the nominal half amplitude
* When configured with a 0.47 F nonpolarized capacitor in series with the TX transformer
primary as shown in Figures A1, A2 and A3.
269 ns
244 ns
194 ns
219 ns
488 ns
Nominal Pulse
Table 4. CCITT G.703 Specifications
For c oax ia l c able,
75
transformer specified
in Application Section.
when RLOOP is selected because the timing cir-
cuitry must adjust to the new frequency.
Transmit All Ones Select
The transmitter provides for all ones insertion at
the frequency of TCLK. Transmit all ones is se-
lected when TAOS goes high, and causes
continuous ones to be transmitted on the line
(TTIP and TRING). In this mode, the TPOS and
TNEG (or TDATA) inputs are ignored. If Remote
Loopback is in effect, any TAOS request will be
ignored.
Receiver
The receiver extracts data and clock from an AMI
(Alternate Mark Inversion) coded signal and out-
puts clock and synchronized data. The receiver is
sensitive to signals over the entire range of
ABAM cable lengths and requires no equalization
or ALBO (Automatic Line Build Out) circuits.
The signal is received on both ends of a center-
tapped, center-grounded transformer. The
transformer is center tapped on the IC side. The
clock and data recovery circuit exceeds the jitter
tolerance specifications of Publications 43802,
43801, AT&T 62411, TR-TSY-000170, and
CCITT REC. G.823.
0 0.237 V
2.37 V
loa d
0.95 to 1.05*
0.95 to 1.05*
a nd
244 ns
For shielded twisted
pair, 120
transformer specified
in Application Section.
CS61574A CS61575
0 0.30 V
3 V
load and
DS154F2