PD45128168G5-A75A-9JF Elpida Memory, Inc., PD45128168G5-A75A-9JF Datasheet - Page 9

• Manufacturer Part Number: PD45128168G5-A75A-9JF
• Description: 128M-bit synchronous DRAM 4-bank, LVTTL MOS integrated circuit
• Manufacturer: Elpida Memory, Inc.

13. Electrical Specifications ................................................................................................................ 34
14. Package Drawing ........................................................................................................................... 85
15. Recommended Soldering Conditions .......................................................................................... 86
16. Revision History ............................................................................................................................. 87
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
13.10 CBR (Auto) Refresh ............................................................................................................................. 51
13.11 Self Refresh (Entry and Exit) .............................................................................................................. 52
13.12 Random Column Read (Page with Same Bank) ............................................................................... 53
13.13 Random Column Write (Page with Same Bank) ............................................................................... 55
13.14 Random Row Read (Ping-Pong Banks) ............................................................................................. 57
13.15 Random Row Write (Ping-Pong Banks) ............................................................................................ 59
13.16 Read and Write .................................................................................................................................... 61
13.17 Interleaved Column Read Cycle ......................................................................................................... 63
13.18 Interleaved Column Write Cycle ......................................................................................................... 65
13.19 Auto Precharge after Read Burst ....................................................................................................... 67
13.20 Auto Precharge after Write Burst ....................................................................................................... 69
13.21 Full Page Read Cycle .......................................................................................................................... 71
13.22 Full Page Write Cycle .......................................................................................................................... 73
13.23 Byte Write Operation ........................................................................................................................... 75
13.24 Burst Read and Single Write (Option) ............................................................................................... 77
13.25 Full Page Random Column Read ....................................................................................................... 79
13.26 Full Page Random Column Write ....................................................................................................... 81
13.27 PRE (Precharge) Termination of Burst .............................................................................................. 83
AC Parameters for Read Timing ......................................................................................................... 39
AC Parameters for Write Timing ........................................................................................................ 41
Relationship between Frequency and Latency ................................................................................. 42
Mode Register Set ............................................................................................................................... 43
Power on Sequence and CBR (Auto) Refresh .................................................................................. 44
/CS Function ........................................................................................................................................ 45
Clock Suspension during Burst Read (using CKE Function) ......................................................... 46
Clock Suspension during Burst Write (using CKE Function) ......................................................... 48
Power Down Mode and Clock Mask .................................................................................................. 50
Data Sheet E0031N30
PD45128441, 45128841, 45128163
9