S1D10605 Epson Electronics America, Inc., S1D10605 Datasheet - Page 94

• Manufacturer Part Number: S1D10605
• Description: S1d15000 Series Lcd Driver With Ram
• Manufacturer: Epson Electronics America, Inc.

S1D15206 Series
Busy Flag
The Busy flag is set when the S1D15206 series starts to operate.
During operating, it accepts Read Status instruction only. The busy
flag signal is output at pin D7 when Read Status is issued. If the cycle
time (
before issuing a command. This can greatly improve the microproc-
essor performance.
Initial Display Line Register
When the display RAM data is read, the display line according to
COM0 (usually, the top line of screen) is determined using register
data. The register is also used for screen scrolling and page
switching.
The Set Display Start Line command sets the 5-bit display start
address in this register. The register data is preset on the line counter
each time FR signal status changes. The line counter is incremented
by oscillator circuit output (in master mode) or CL input (in slave
mode), and it generates a line address to allow 80-bit sequential data
output from display RAM to LCD driver circuit.
Column Address Counter
This is a 7-bit presettable counter that provides column address to the
display RAM (refer to Figure 4). It is incremented by 1 when a Read/
Write command is entered. However, the counter is not incremented
but locked if a non-existing address above 50H is specified. It is
4–10
t
cyc
) is correct, the microprocessor needs not to check the flag
D0
D1
D2
D3
D4
1
0
1
0
0
Display data RAM
EPSON
Figure 3
unlocked when a column address is set again. The Column Address
counter is independent of Page Address register.
When ADC Select command is issued to display inverse display, the
column address decoder inverts the relationship between RAM
column address and display segment output.
Page Address Register
This is a 4-bit page address register that provides page address to the
display RAM (refer to Figure 4). The microprocessor issues Set
Page Address command to change the page and access to another
page. Page address 4 (D2 is high, but D0 and D1 are low) is RAM
area dedicate to the indicator, and display data D0 is only valid.
Display Data RAM
The display data RAM stores pixel data for LCD. It is a 33-column
by 80-row (4-page by 8+1 bit) addressable array. Each pixel can be
selected when page and column addresses are specified.
The time required to transfer data is very short because the micro-
processor enters D0 to D7 corresponding to LCD common lines as
shown in Figure 3. Therefore, multiple S1D15206’s can easily
configure a large display having the high flexibility with very few
data transmission restriction.
The microprocessor writes and reads data to/from the RAM through
I/O buffer. As LCD controller operates independently, data can be
written into RAM at the same time as data is being displayed,
without causing the LCD to flicker.
COM0
COM1
COM2
COM3
COM4
Display on LCD
Rev.3.5