N25Q128 Numonyx, N25Q128 Datasheet - Page 107

• Manufacturer Part Number: N25Q128
• Description: 128-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase On Boot Sectors, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

9.1.28
9.1.29
S
C
DQ0
DQ1
Figure 35. Clear Flag Status Register instruction sequence
Read NV Configuration Register
The Read Non Volatile Configuration Register (RDNVCR) instruction allows the Non Volatile
Configuration Register to be read.
Figure 36. Read NV Configuration Register instruction sequence
Write NV Configuration Register
The Write Non Volatile Configuration register (WRNVCR) instruction allows new values to
be written to the Non Volatile Configuration register. Before it can be accepted, a write
enable (WREN) instruction must previously have been executed. After the write enable
(WREN) instruction has been decoded and executed, the device sets the write enable latch
(WEL).
The Write Non Volatile Configuration register (WRNVCR) instruction is entered by driving
Chip Select (S) Low, followed by the instruction code and the data bytes on serial data input
(DQ0).
Chip Select (S) must be driven High after the 16th bit of the data bytes has been latched in.
If not, the Write Non Volatile Configuration register (WRNVCR) instruction is not executed.
0
High Impedance
S
C
DQ0
DQ1
1
2
Instruction
3
4
5
0
6
1
7
High Impedance
7
2
8
Instruction
6
3
9 10 11 12 13 14 15
5
4
NVCR Out
LS Byte
4
5
3
6
2
7
MSB
1
8
0
15 14 13 12 11 10 9
16 17 18 19 20 21 22 23
NVCR Out
MS Byte
Clear_Flag_SR
8
Read_NVCR
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