N25Q128 Numonyx, N25Q128 Datasheet - Page 80

• Manufacturer Part Number: N25Q128
• Description: 128-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase On Boot Sectors, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

Table 15.
Table 16.
Figure 10. Read identification instruction and data-out sequence
9.1.2
80/180
20h
Reserved Reserved Reserved
Bit 7
Manufacturer
Identification
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the Standby Power mode, the device waits to be selected, so that it can receive, decode and
execute instructions.
Read Identification data-out sequence
Extended Device ID table (first byte)
Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on Serial Data output (DQ1), each bit being shifted out, at a
maximum frequency fR, during the falling edge of Serial Clock (C).
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)
Bit 6
Memory type
BAh
Bit 5
Device identification
VCR XIP bit setting:
0 = required,
1 = not required
Memory capacity
18h
Bit 4
Hold/Reset function:
0 = HOLD,
1 = Reset
EDID+CFD length
10h
Bit 3
Addressing:
0 = by Byte,
EDID
2 bytes
Bit 2
UID
Architecture:
00 = Uniform,
01 = Bottom,
11 = Top
CFD
14 bytes
Bit 1
Bit 0