UMA1015AM NXP Semiconductors, UMA1015AM Datasheet - Page 4

• Manufacturer Part Number: UMA1015AM
• Description: Low-power Dual Frequency Synthesizer For Radio Communications
• Manufacturer: NXP Semiconductors

Philips Semiconductors
PINNING
FUNCTIONAL DESCRIPTION
Main dividers
Each synthesizer has a fully programmable 17-bit main
divider. The RF input drives a pre-amplifier to provide the
clock to the first divider bit. The pre-amplifier has a high
input impedance, dominated by pin and pad capacitance.
The circuit operates with signal levels from below
50 mV (RMS) up to 250 mV (RMS), and at frequencies up
to 1.1 GHz. The high frequency sections of the divider are
implemented using bipolar transistors, while the slower
section uses CMOS technology. The range of division
ratios is 512 to 131071.
Reference divider
There is a common fully programmable 12-bit reference
divider for the two synthesizers. The input f
pre-amplifier to provide the clock input for the reference
1997 Sep 03
P1
P2
CPA
V
HPD
RFA
DGND
f
P3
f
CLK
DATA
E
V
RFB
AGND
CPB
V
P0/OOL
I
SYMBOL
XTALIN
XTALO
SET
DD1
DD2
CC
Low-power dual frequency synthesizer
for radio communications
PIN
12
10
11
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
output Port 1
output Port 2
charge pump output synthesizer A
digital supply voltage 1
hardware power-down
(input LOW = power-down)
RF input synthesizer A
digital ground
common crystal frequency input from
TCXO
output Port 3
open-drain output of f
programming bus clock input
programming bus data input
programming bus enable input
(active LOW)
digital supply voltage 2
RF input synthesizer B
analog ground to charge pumps
charge pump output synthesizer B
analog supply to charge pump;
external or voltage doubler output
Port output 0/out-of-lock output
regulator pin to set charge pump
currents
DESCRIPTION
XTAL
XTALIN
signal
drives a
4
divider. This clock signal is also inverted and output on pin
f
and f
used to make an oscillator. An extra divide-by-2 block
allows a reference comparison frequency for
synthesizer B to be half the frequency of synthesizer A.
This feature is selectable using the program bit SR. If the
programmed reference divider ratio is R then the ratio for
each synthesizer is as given in Table 1.
The range for the division ratio R is 8 to 4095. Opposite
edges of the divider output are used to drive the phase
detectors to ensure that active edges arrive at the phase
detectors of each synthesizer at different times. This
minimizes the potential for interference between the
charge pumps of each loop. The reference divider consists
of CMOS devices operating beyond 35 MHz.
XTALO
handbook, halfpage
XTALO
(open drain). A crystal connected between f
with suitable feedback components can be
f XTALIN
f XTALO
DGND
V DD1
HPD
CPA
RFA
P1
P2
P3
Fig.2 Pin configuration.
10
1
2
3
4
5
6
7
8
9
UMA1015AM
MGG522
UMA1015AM
15
14
13
12
19
18
17
16
11
20
Product specification
I SET
P0/OOL
V CC
CPB
AGND
RFB
V DD2
E
DATA
CLK
XTALIN