ST7036 ETC-unknow, ST7036 Datasheet - Page 17

• Manufacturer Part Number: ST7036
• Description: Dot Matrix Lcd Controller/driver
• Manufacturer: ETC-unknow

ST7036
During write operation, two 8-bit registers are used. One is data register (DR), the other is instruction
register(IR).
The data register(DR) is used as temporary data storage place for being written into DDRAM/CGRAM/ICON
RAM, target RAM is selected by RAM address setting instruction. Each internal operation, writing into RAM, is
done automatically. So to speak, after MPU writes data to DR, the data in DR is transferred into
DDRAM/CGRAM/ICON RAM automatically.
The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to
read instruction data.
To select register, use RS bit input in IIC interface.
When BF = "High”, it indicates that the internal operation is being processed. So during this time the next
instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation),
through DB7 port. Before executing the next instruction, be sure that BF is not High.
Address Counter(AC) stores DDRAM/CGRAM/ICON RAM address, transferred from IR.
After writing into (reading from) DDRAM/CGRAM/ICON RAM, AC is automatically increased (decreased) by 1.
When RS = "Low" and R/W = "High", AC can be read through DB0 ~ DB6 ports.
V1.1
Busy Flag (BF)
Address Counter (AC)
Co
S 0 1 1 1 1
RS R/W
Write mode
0
1
H
L
slave address
Last control byte to be sent. Only a stream of data bytes is allowed to follow.
This stream may only be terminated by a STOP condition.
Another control byte will follow the data byte unless a STOP condition is received.
L
L
Table 2. Various kinds of operations according to RS and R/W bits.
acknowledgement
0 1 1 1 1
1 0
from ST7036i
Instruction Write operation (MPU writes Instruction code into IR)
Data Write operation (MPU writes data into DR)
slave address
R/W
0 A
Co
1
R
S
1 0
Ã
control byte
W
R
/
acknowledgement
from ST7036i
command word
2n>=0 bytes
Fig .5 IIC Interface protocol
A
C
o
R
S
control byte
0 0 0 0 0 0
data byte
17/72
acknowledgement
Operation
from ST7036i
A
Co
0
R
S
control byte
1 byte
D
7
acknowledgement
D
6
from ST7036i
D
5
data byte
D
4
A
MSB.......................LSB
D
3
D
2
D
1
n>=0 bytes
D
0
data byte
acknowledgement
from ST7036i
A P
2003/12/24