DSPIC30F4012 Microchip Technology Inc., DSPIC30F4012 Datasheet - Page 109

• Manufacturer Part Number: DSPIC30F4012
• Description: Dspic30f4011/4012 Enhanced Flash 16-bit Digital Signal Controller
• Manufacturer: Microchip Technology Inc.

17.0
The Inter-Integrated Circuit (I
complete hardware support for both Slave and Multi-
Master modes of the I
standard with a 16-bit interface.
This module offers the following key features:
• I
• I
• I
• I
• Serial Clock Synchronization for I
• I
17.1
The hardware fully implements all the master and slave
functions of the I
Thus, the I
a master on an I
FIGURE 17-1:
© 2007 Microchip Technology Inc.
specifications, as well as 7 and 10-bit addressing.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the dsPIC30F Family Reference
Manual (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
Operation.
Master and Slaves.
used as a Handshake Mechanism to Suspend
and Resume Serial Transfer (SCLREL control).
Collision and will Arbitrate accordingly.
2
2
2
2
2
C Interface supporting both Master and Slave
C Slave mode supports 7 and 10-bit addressing.
C Master mode supports 7 and 10-bit addressing.
C Port allows Bidirectional Transfers between
C supports Multi-Master Operation; Detects Bus
I
Operating Function Description
2
2
C™ MODULE
C module can operate either as a slave or
2
C bus.
2
C Standard and Fast mode
PROGRAMMER’S MODEL
bit 15
bit 15
2
C serial communication
2
C) module provides
2
C Port can be
bit 9
bit 8
bit 7
bit 7
17.1.1
The following types of I
• I
• I
• I
See the I
17.1.2
I
is data.
17.1.3
I2CCON and I2CSTAT are control and status registers,
respectively. The I2CCON register is readable and writ-
able. The lower 6 bits of I2CSTAT are read-only. The
remaining bits of the I2CSTAT are read/write.
I2CRSR is the shift register used for shifting data,
whereas I2CRCV is the buffer register to which data
bytes are written or from which data bytes are read.
I2CRCV is the receive buffer, as shown in Figure 17-1.
I2CTRN is the transmit register to which bytes are
written during a transmit operation, as shown in
Figure 17-2.
The I2CADD register holds the slave address. A status
bit, ADD10, indicates 10-bit Address mode. The
I2CBRG acts as the Baud Rate Generator reload
value.
In receive operations, I2CRSR and I2CRCV together
form a double-buffered receiver. When I2CRSR
receives a complete byte, it is transferred to I2CRCV
and
transmission, the I2CTRN is not double-buffered.
2
C has a 2-pin interface; SCL pin is clock and SDA pin
Note:
2
2
2
dsPIC30F4011/4012
C slave operation with 7-bit addressing.
C slave operation with 10-bit addressing.
C master operation with 7 or 10-bit addressing.
an
2
C programmer’s model in Figure 17-1.
bit 0
bit 0
bit 0
bit 0
bit 0
bit 0
interrupt
VARIOUS I
PIN CONFIGURATION IN I
I
Following a Restart condition in 10-bit
mode, the user only needs to match the
first 7-bit address.
2
C REGISTERS
I2CRCV (8 bits)
I2CTRN (8 bits)
I2CBRG (9 bits)
I2CCON (16-bits)
I2CSTAT (16-bits)
I2CADD (10-bits)
pulse
2
C operation are supported:
2
C MODES
is
generated.
DS70135E-page 107
2
C MODE
During