DSPIC30F4012 Microchip Technology Inc., DSPIC30F4012 Datasheet - Page 142

• Manufacturer Part Number: DSPIC30F4012
• Description: Dspic30f4011/4012 Enhanced Flash 16-bit Digital Signal Controller
• Manufacturer: Microchip Technology Inc.

combine to directly affect the time required to charge the
dsPIC30F4011/4012
20.8
The analog input model of the 10-bit ADC is shown in
Figure 20-3. The total sampling time for the ADC is a
function of the internal amplifier settling time, device
V
For the ADC to meet its specified accuracy, the charge
holding capacitor (C
charge to the voltage level on the analog input pin. The
source impedance (R
(R
capacitor C
log sources must therefore be small enough to fully
charge the holding capacitor within the chosen sample
time. To minimize the effects of pin leakage currents on
the accuracy of the ADC, the maximum recommended
source impedance, R
channel is selected (changed), this sampling function
must be completed prior to starting the conversion. The
internal holding capacitor will be in a discharged state
prior to each sample operation.
FIGURE 20-3:
DS70135E-page 140
DD
IC
) and the internal sampling switch (R
and the holding capacitor charge time.
A/D Acquisition Requirements
HOLD
Note: C
. The combined impedance of the ana-
Legend: C
VA
HOLD
S
Rs
PIN
S
, is 5 kΩ. After the analog input
A/D CONVERTER ANALOG INPUT MODEL
), the interconnect impedance
value depends on device package and is not tested. Effect of C
V
I leakage
R
R
C
) must be allowed to fully
ANx
PIN
T
IC
SS
HOLD
C
PIN
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch Resistance
= Sample/Hold Capacitance (from DAC)
various junctions
SS
) impedance
V
DD
V
V
T
T
= 0.6V
= 0.6V
R
I
±500 nA
LEAKAGE
IC
≤ 250Ω
The user must allow at least 1 T
time, T
ple to be acquired. This sample time may be controlled
manually in software by setting/clearing the SAMP bit,
or it may be automatically controlled by the ADC. In an
automatic configuration, the user must allow enough
time between conversion triggers so that the minimum
sample time can be satisfied. Refer to Section 24.0
“Electrical Characteristics” for T
requirements.
SAMP
Sampling
Switch
R
, between conversions to allow each sam-
SS
PIN
R
negligible if Rs ≤ 5 kΩ.
SS
V
SS
C
= DAC Capacitance
= 4.4 pF
≤ 3 kΩ
HOLD
© 2007 Microchip Technology Inc.
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period of sampling
and sample time