ACS8515REV2.1 Semtech Corporation, ACS8515REV2.1 Datasheet - Page 9

• Manufacturer Part Number: ACS8515REV2.1
• Description: Line Card Protection Switch for Sonet or SDH Network Elements
• Manufacturer: Semtech Corporation

Table 4. Input Reference Source Selection and Group Allocation
Table 4. Input Reference Source Selection and Group Allocation
Table 4. Input Reference Source Selection and Group Allocation
Table 4. Input Reference Source Selection and Group Allocation
Table 4. Input Reference Source Selection and Group Allocation
2. Any multiple of any supported frequency can be
supported by using the "DivN" feature (bit 7 of the
cnfg_ref_source_frequency register). Any reference input
can be set to lock at 8 kHz independently of the
frequencies and configurations of the other inputs.
Any reference input with the ‘DivN’ bit set in
the cnfg_ref_source_frequency register will
employ the internal pre-divider prior to the DPLL
locking. The cnfg_freq_divn register contains
the divider ratio N where the reference input
will get divided by (N+1) where 0<N<2
cnfg_ref_source_frequency register must be set
to the closest supported spot frequency to the
input frequency, but must be lower than the
Revision 2.01/December 2005 Semtech Corp.
ADVANCED COMMUNICATIONS
Notes for Table 4.
Notes for Table 4.
Notes for Table 4.
Notes for Table 4.
Notes for Table 4.
Note 1. TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency
being 77.76 MHz. The actual spot frequencies are 2 kHz, 4 kHz, 8 kHz, N x 8 kHz, 1.544/2.048 MHz, 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz and 77.76 MHz.
Note 2. PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz. There are different output
clock frequencies available for SONET and SDH applications.
Note 3. The default priority values in brackets are the default numbers reported in the register map, which match up with the
ACS8510.
On power up, or by reset, the default will be set by the SONSDHB pin. Specific frequencies and priorities are set by
configuration. For SONET, config_mode register 34 Hex, bit 2 = 1. For SDH config_mode register 34 Hex, bit 2 = 0.
P
P
P
P
P
o
o
o
o
o
t r
t r
t r
t r
t r
S
S
S
S
S
S
Y
E
E
E
E
E
N
N
N
N
N
N
C
C
C
C
C
C
1
2
1
2
3
a
a
a
a
a
1
m
m
m
m
m
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e
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P
T
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T
T
E
p
p
p
p
p
h c
h c
h c
h c
h c
E
L T
L T
D
L T
L T
C
D
C
t u
t u
t u
t u
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S
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n
n
n
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d
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p
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p
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u a
u a
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o t
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t l
t l
t l
t l
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1
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1
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F
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input frequency. When using the ‘DivN’ feature
the post-divider frequency must be 8 kHz, which
is indicated by setting the ‘lock8k’ bit high (bit
6 in cnfg_ref_source_frequency register). Any
input set to DivN must have the frequency
monitors disabled (if the frequency monitors
are disabled, they are disabled for all inputs
regardless of the input configurations, in this
case only activity monitoring will take place).
Whilst any number of inputs can be set to use
the ‘DivN’ feature, only one N can be
programmed, hence all inputs using the ‘DivN’
feature must require the same division to get
to 8 kHz.
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p
p
p
p
p
p
p
p
p
p
8
8
1
1
1
ACS8515 Rev2.1 LC/P
r o
r o
r o
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k
k
9
9
9
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4 .
4 .
4 .
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4
4
4
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d
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S
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E
E
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E
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C
C
C
C
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r u
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3
1
2
1
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G
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o r
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p
p
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D
D
D
D
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r P
r P
r P
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FINAL
3
4
1
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u
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