ACS8510REV2.1 Semtech Corporation, ACS8510REV2.1 Datasheet

ACS8510REV2.1

Manufacturer Part Number

ACS8510REV2.1

Description

Synchronous Equipment Timing Source for Sonet or SDH Network Elements

Manufacturer

Semtech Corporation

Datasheet

1.ACS8510REV2.1.pdf (76 pages)

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The ACS8510 is a highly integrated, single-chip

solution for the Synchronous Equipment Timing

Source (SETS) function in a SONET or SDH Net-

work Element. The device generates SONET or

SDH Equipment Clocks (SEC) and frame synchro-

nization clocks. The ACS8510 is fully compliant

with the required specifications and standards.

The device supports Free-run, Locked and

Holdover modes. It also supports all three types

of reference clock source: recovered line clock,

PDH network, and node synchronization. The

ACS8510 generates independent SEC and BITS

clocks, an 8 kHz Frame Synchronization clock

and a 2 kHz Multi-Frame Synchronization clock.

Two ACS8510 devices can be used together in a

Master/Slave configuration mode allowing sys-

tem protection against a single ACS8510 failure.

A microprocessor port is incorporated, providing

access to the configuration and status registers

for device setup and monitoring. The ACS8510

supports IEEE 1149.1 JTAG boundary scan.

Rev2.1 adds choice of edge alignment for 8kHz

input, as well as a low jitter n x E1/DS1 output

mode. Other minor changes are made, with all

described in Appendix A.

Revision 2.00/September 2003

Figure 1. Simple Block Diagram

ADVANCED COMMUNICATIONS

Block Diagram

Description

2 x PECL/LVDS

1.544/2.048MHz

Programmable;

TCK

TDI

TMS

TRST

TDO

155.52MHz

19.44MHz

25.92MHz

38.88MHz

51.84MHz

77.76MHz

10 x TTL

N x 8kHz

6.48MHz

2 x AMI

64/8kHz

2kHz

4kHz

14xSEC

MFrSync

Input

Ports

1149.1

JTAG

IEEE

TCXO (*OCXO)

Monitors

selector

Chip Clock

Generator

OUT4

OUT0

Semtech Corp.

Divider

Priority

Table

DPLL/Freq. Synthesis

PFD

Set

PFD

Digital

Filter

Loop

S S S S S ynchronous E E E E E quipment T T T T T iming S S S S S ource

DPLL/Freq. Synthesis

•Suitable for Stratum 3E*, 3, 4E and 4 SONET

•Meets AT&T, ITU-T, ETSI and Telcordia

•Accepts 14 individual input reference clocks

•Generates 11 output clocks

•Supports Free-run, Locked and Holdover

•Robust input clock source quality monitoring on

•Automatic ‘hit-less’ source switchover on loss

•Phase build out for output clock phase

•Microprocessor interface - Intel, Motorola,

•Programmable wander and jitter tracking

•Support for Master/Slave device configuration

•IEEE 1149.1 JTAG Boundary Scan

•Single +3.3 V operation, +5 V I/O compatible

•Operating temperature (ambient) -40°C to

•Available in 100 pin LQFP package

* Meets Holdover requirements, lowest bandwidth 0.1 Hz.

+85°C

all inputs

Serial, Multiplexed, EPROM

Features

of input

continuity during input switchover and mode

for SONET or SDH Network Elements

or SDH Equipment Clock (SEC) applications

specifications

modes of operation

transitions

attenuation 0.1 Hz to 20 Hz

alignment and hot/standby redundancy

Digital

ACS8510 Rev2.1 SETS

Loop

Filter

Microprocessor

DTO

Port

DTO

Frequency

Dividers

APLL

Output

FrSync

MFrSync

9xSEC

Ports

www.semtech.com

1 x AMI

6 x TTL

2 x PECL/LVDS

Programmable:

64/8kHz

1.544/2.048MHz

3.088/4.096MHz

6.176/8.182MHz

12.352/16.384MHz

6.48MHz

19.44MHz

25.92MHz

38.88MHz

51.84MHz

77.76MHz

155.52MHz

311.04MHz

2kHz MFrSync

8kHz FrSync

FINAL

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