ACS8510REV2.1 Semtech Corporation, ACS8510REV2.1 Datasheet - Page 22

• Manufacturer Part Number: ACS8510REV2.1
• Description: Synchronous Equipment Timing Source for Sonet or SDH Network Elements
• Manufacturer: Semtech Corporation

Register Set
Register Set
Configuration Registers
Configuration Registers
Status Registers
Status Registers
Register Access
Register Access
from the ROM is used to set the internal register
values. Only 64 locations in the ROM are
required.
Register Set
Register Set
Register Set
All registers are 8-bits wide, organised with the
most-significant bit positioned in the left-most
bit, with bit significance decreasing towards the
right most bit. Some registers carry several
individual data fields of various sizes, from
single-bit values (e.g. flags) upwards. Several
data fields are spread across multiple registers;
their organisation is shown in the register map,
Table 11.
Configuration Registers
Configuration Registers
Configuration Registers
Each configuration register reverts to a default
value on power-up or following a reset. Most
default values are fixed, but some will be pin-
settable. All configuration registers can be read
out over the microprocessor port.
Status Registers
Status Registers
Status Registers
The Status Registers contain readable registers.
They may all be read from outside the chip but
are not writeable from outside the chip (except
for a clearing operation). All status registers
are read via shadow registers to avoid data
hits due to dynamic operation. Each individual
status register has a unique location.
Register Access
Register Access
Register Access
Most registers are of one of two types,
configuration registers or status registers, the
exceptions being the chip_ID and chip_revision
registers. Configuration registers may be written
to or read from at any time (the complete 8-bit
register must be written, even if only one bit is
being modified). All status registers may be read
at any time and, in some status registers (such
as the sts_interrupts register), any individual
data field may be cleared by writing a ‘1’ into
each bit of the field (writing a ‘0’ value into a
bit will not affect the value of the bit). A
description of each register is given in the
Register Map, and Register Map Description.
Revision 2.00/September 2003
ADVANCED COMMUNICATIONS
Semtech Corp.
22
Interrupt Enable and Clear
Interrupt Enable and Clear
Interrupt Enable and Clear
Interrupt Enable and Clear
Interrupt Enable and Clear
Interrupt requests are flagged on pin INTREQ
(active High). Bits in the interrupt status register
are set (high) by the following conditions:
1. Any reference source becoming valid or going invalid
2. A change in the operating state (eg. Locked, Holdover
etc.)
3. A brief loss of the currently selected reference source
4. An AMI input error
All interrupt sources are maskable via the mask
register, each one being enabled by writing a
'1' to the appropriate bit. Any unmasked bit set
in the interrupt status register will cause the
interrupt request pin to be asserted (high). All
interrupts are cleared by writing a '1' to the
bit(s) to be cleared in the status register. When
all pending unmasked interrupts are cleared
the interrupt pin will go inactive (low).
The loss of the currently selected reference
source will eventually cause the input to be
considered invalid, triggering an interrupt. The
time taken to raise this interrupt is dependant
on the leaky bucket configuration of the activity
monitors. The fastest leaky bucket setting will
still take up to 128 ms to trigger the interrupt.
The interrupt caused by the brief loss of the
currently selected reference source is provided
to facilitate very fast source failure detection if
desired.
couple of cycles of the reference source. Some
applications require the facility to switch
downstream devices based on the status of
the reference sources. In order to provide extra
flexibility, it is possible to flag the ‘main
reference failed’ interrupt (addr 06, bit 6) on
the pin TDO. This is simply a copy of the status
bit in the interrupt register and is independent
of the mask register settings.
by writing to the interrupt status register in the
normal way. This feature can be enabled and
disabled by writing to bit 6 of register 48Hex.
ACS8510 Rev2.1 SETS
It is triggered after missing just a
The bit is reset
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