LFECP40 Lattice Semiconductor, LFECP40 Datasheet
LFECP40
Related parts for LFECP40
LFECP40 Summary of contents
Page 1
LatticeECP/EC Family Data Sheet Version 01.3 ...
Page 2
... Introduction Preliminary Data Sheet LFEC20/ LFEC33/ LFEC40/ LFECP20 LFECP33 LFECP40 1920 2464 4096 5120 15.4 19.7 32.8 41 131 350 424 535 1.2 1 ...
Page 3
... Lattice Semiconductor Introduction The LatticeECP/EC family of FPGA devices has been optimized to deliver mainstream FPGA features at low cost. For maximum performance and value, the LatticeECP (EConomy Plus) FPGA concept combines an efficient FPGA fabric with high-speed dedicated functions. Lattice’s first family to implement this approach is the LatticeECP-DSP (EConomy Plus DSP) family, providing dedicated high-performance DSP blocks on-chip. The LatticeEC™ ...
Page 4
... The LatticeECP/EC devices use 1.2V as their core volt- age. © 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 5
... Lattice Semiconductor Figure 2-1. Simplified Block Diagram, LatticeECP/EC Device (Top Level) Programmable I/O Cell (PIC) includes sysIO Interface sysCONFIG Programming Port (includes dedicated and dual use pins) Programmable Functional Unit (PFU) Figure 2-2. Simplified Block Diagram, LatticeECP-DSP Device (Top Level) Programmable I/O Cell ...
Page 6
... Lattice Semiconductor PFU and PFF Blocks The core of the LatticeECP/EC devices consists of PFU and PFF blocks. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term PFU to refer to both PFU and PFF blocks ...
Page 7
... Lattice Semiconductor Figure 2-4. Slice Diagram From M1 Routing Control Signals CE selected and CLK inverted per LSR slice in routing Interslice signals are not shown Table 2-1. Slice Signal Descriptions Function Type Input Data signal Input Data signal Input Multi-purpose Input ...
Page 8
... Lattice Semiconductor Modes of Operation Each Slice is capable of four modes of operation: Logic, Ripple, RAM and ROM. The Slice in the PFF is capable of all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks. Table 2-2. Slice Modes PFU Slice LUT 4x2 or LUT 5x1 ...
Page 9
... Lattice Semiconductor Figure 2-5. Distributed Memory Primitives SPR16x2 AD0 AD1 AD2 AD3 DI0 DI1 WRE CK ROM16x1 AD0 AD1 AD2 AD3 ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is accomplished through the programming interface during configuration. ...
Page 10
... Lattice Semiconductor Routing There are many resources provided in the LatticeECP/EC devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU). ...
Page 11
... Lattice Semiconductor Secondary Clock Sources LatticeECP/EC devices have four secondary clock resources per quadrant. The secondary clock branches are tapped at every PFU. These secondary clock networks can also be used for controls and high fanout data. These secondary clocks are derived from four clock input pads and 16 routing signals as shown in Figure 2-7. ...
Page 12
... Lattice Semiconductor Figure 2-8. Per Quadrant Primary Clock Selection 20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing 4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant 1. Smaller devices have fewer PLL related lines. Figure 2-9. Per Quadrant Secondary Clock Selection 20 Secondary Clock Feedlines : 4 Clock Input Pads + 16 Routing Signals Figure 2-10 ...
Page 13
... Lattice Semiconductor adjustment and not relock until the t allows the user to adjust the phase and duty cycle of the CLKOS output. The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated with it: input clock divider, feedback divider, post scalar divider and secondary clock divider. The input clock divider is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal ...
Page 14
... Lattice Semiconductor Table 2-5. PLL Signal Descriptions Signal I/O CLKI I Clock input from external pin or routing CLKFB I PLL feedback input from CLKOP, clocknet, or external pin RST I “1” to reset PLL CLKOS O PLL output clock to clock tree (phase shifted/duty cycle changed) CLKOP O PLL output clock to clock tree (No phase shift) ...
Page 15
... Lattice Semiconductor Figure 2-14. DCS Waveforms CLK0 CLK1 SEL DCSOUT sysMEM Memory The LatticeECP/EC family of devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR con- sists of a 9-Kbit RAM, with dedicated input and output registers. sysMEM Memory Block The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a variety of depths and widths as shown in Table 2-6. Table 2-6. sysMEM Block Confi ...
Page 16
... Lattice Semiconductor Memory Cascading Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. Single, Dual and Pseudo-Dual Port Modes Figure 2-15 shows the four basic memory configurations and their input/output names. In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory array ...
Page 17
... Lattice Semiconductor Figure 2-16. Memory Core Reset RSTA RSTB GSRN For further information on sysMEM EBR block, please see the details of additional technical documentation at the end of this data sheet. sysDSP Block The LatticeECP-DSP family provides a sysDSP block making it ideally suited for low cost, high performance Digital Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response (FIR) fi ...
Page 18
... Lattice Semiconductor Figure 2-17. Comparison of General DSP and LatticeECP-DSP Approaches Operand Operand A B Single x Multiplier Σ Accumulator Function implemented in General purpose DSP sysDSP Block Capabilities The sysDSP block in the LatticeECP-DSP family supports four functional elements in three 9, 18 and 36 data path widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned) of its operands ...
Page 19
... Lattice Semiconductor MULT sysDSP Element This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B, are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers. Figure 2-18 shows the MULT sysDSP element. ...
Page 20
... Lattice Semiconductor MULTADD sysDSP Element In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi- plier operation of operands A1 and A2. The user can enable the input, output and pipeline registers. Figure 2-20 shows the MULTADD sysDSP element. ...
Page 21
... Lattice Semiconductor Figure 2-21. MULTADDSUM Shift Register B In Multiplicand A0 n Multiplier Input Data Register B n Multiplicand A1 Multiplier Input Data Register B Multiplicand A2 n Multiplier Input Data Register B n Multiplicand A3 Multiplier Input Data Register B Signed n Addn0 Addn1 Shift Register B Out Clock, Clock Enable and Reset Resources Global Clock, Clock Enable and Reset signals from routing are available to every DSP block ...
Page 22
... Lattice Semiconductor Table 2-8. An Example of Sign Extension Unsigned Number Unsigned 9-bit +5 0101 000000101 -6 0110 000000110 OVERFLOW Flag from MAC The sysDSP block provides an overflow output to indicate that the accumulator has overflowed. When two unsigned numbers are added and the result is a smaller number then accumulator roll over is said to occur and overfl ...
Page 23
... Table 2-11 lists the maximum performance in millions of MAC operations per second (MMAC) for each member of the LatticeECP family. Table 2-11. DSP Block Performance of LatticeECP Family LFECP10 LFECP15 LFECP20 LFECP33 LFECP40 For further information on the sysDSP block, please see details of additional technical information at the end of this data sheet. 9x9 Multiplier ...
Page 24
... Lattice Semiconductor Programmable I/O Cells (PIC) Each PIC contains two PIOs connected to their respective sysIO Buffers which are then connected to the PADs as shown in Figure 2-23. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to sysIO buffer, and receives input from the buffer. ...
Page 25
... Lattice Semiconductor Table 2-12. PIO Signal List Name CE0, CE1 Control from the core CLK0, CLK1 Control from the core LSR Control from the core GSRN Control from routing INCK Input to the core DQS Input to PIO INDD Input to the core INFF Input to the core ...
Page 26
... Lattice Semiconductor Input Register Block The input register block contains delay elements and registers that can be used to condition signals before they are passed to the device core. Figure 2-25 shows the diagram of the input register block. Input signals are fed from the sysIO buffer to the input register block (as signal DI). If desired the input signal can bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and in selected blocks the input to the DQS delay block. If one of the bypass options is not chosen, the signal fi ...
Page 27
... Lattice Semiconductor Figure 2-26. Input Register DDR Waveforms DI (In DDR Mode) DQS DQS Delayed D0 D2 Figure 2-27. INDDRXB Primitive Output Register Block The output register block provides the ability to register signals from the core of the device before they are passed to the sysIO buffers. The block contains a register for SDR operation that is combined with an additional latch for DDR operation. Figure 2-28 shows the diagram of the Output Register Block. In SDR mode, ONEG0 feeds one of the fl ...
Page 28
... Lattice Semiconductor Figure 2-28. Output Register Block ONEG0 From Routing OPOS0 CLK1 Figure 2-29. ODDRXB Primitive Tristate Register Block The tristate register block provides the ability to register tri-state control signals from the core of the device before they are passed to the sysIO buffers. The block contains a register for SDR operation and an additional latch for DDR operation. Figure 2-30 shows the diagram of the Tristate Register Block. In SDR mode, ONEG1 feeds one of the fl ...
Page 29
... Lattice Semiconductor Figure 2-30. Tristate Register Block TD ONEG1 From Routing OPOS1 CLK1 Control Logic Block The control logic block allows the selection and modification of control signals for use in the PIO block. A clock is selected from one of the clock signals provided from the general purpose routing and a DQS signal provided from the programmable DQS pin ...
Page 30
... Lattice Semiconductor Figure 2-31. DQS Local Bus. Delay Control Bus Polarity Control Bus DQS Bus DQS DQS Figure 2-32. DLL Calibration Bus and DQS/DQS Transition Distribution Delay Control Bus LatticeECP/EC Family Data Sheet PIO Input Register Block ( 5 Flip Flops) To Sync. Reg. GSR CLKI ...
Page 31
... Lattice Semiconductor Polarity Control Logic In a typical DDR Memory interface design, the phase relation between the incoming delayed DQS strobe and the internal system Clock (during the READ cycle) is unknown. The LatticeECP/EC family contains dedicated circuits to transfer data between these domains. To prevent setup and hold violations at the domain transfer between DQS (delayed) and the system Clock a clock polarity selector is used ...
Page 32
... Lattice Semiconductor Figure 2-33. LatticeECP/EC Banks V CCIO7 V REF1(7) V REF2(7) GND V CCIO6 V REF1(6) V REF2(6) GND Note: N and M are the maximum number of I/Os per bank. LatticeECP/EC devices contain two types of sysIO buffer pairs. 1. Top and Bottom sysIO Buffer Pair (Single-Ended Outputs Only) The sysIO buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also be confi ...
Page 33
... Lattice Semiconductor options for drive strength, bus maintenance (weak pull-up, weak pull-down bus-keeper latch) and open drain. Other single-ended standards supported include SSTL and HSTL. Differential standards supported include LVDS, BLVDS, LVPECL, RSDS, differential SSTL and differential HSTL. Tables 2-13 and 2-14 show the I/O standards (together with their supply and reference voltages) supported by the LatticeECP/EC devices ...
Page 34
... Lattice Semiconductor Table 2-14. Supported Output Standards Output Standard Single-ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVCMOS33, Open Drain LVCMOS25, Open Drain LVCMOS18, Open Drain LVCMOS15, Open Drain LVCMOS12, Open Drain PCI33 HSTL18 Class I, II, III HSTL15 Class I, III SSTL3 Class I, II ...
Page 35
... Lattice Semiconductor Configuration and Testing The following section describes the configuration and testing features of the LatticeECP/EC family of devices. IEEE 1149.1-Compliant Boundary Scan Testability All LatticeECP/EC devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access port (TAP) ...
Page 36
... Lattice Semiconductor Oscillator Every LatticeECP/EC device has an internal CMOS oscillator which is used to derive a master serial clock for con- figuration. The oscillator and the master serial clock run continuously. The default value of the master serial clock is 2.5MHz. Table 2-15 lists all the available Master Serial Clock frequencies. When a different Master Serial Clock is selected during the design process, the following sequence takes place: 1 ...
Page 37
... LVCMOS and LVTTL only. © 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 38
... Lattice Semiconductor DC Electrical Characteristics Symbol Parameter Input or I/O Low leakage IL I/O Active Pull-up Current PU I I/O Active Pull-down Current PD I Bus Hold Low sustaining current BHLS I Bus Hold High sustaining current V BHHS I Bus Hold Low Overdrive current BHLO I Bus Hold High Overdrive current ...
Page 39
... LFECP10/LFEC10 LFECP15/LFEC15 LFECP20/LFEC20 LFECP33/LFEC33 LFECP40/LFEC40 LFEC1 LFEC3 LFECP6/LFEC6 LFECP10/LFEC10 LFECP15/LFEC15 LFECP20/LFEC20 LFECP33/LFEC33 LFECP40/LFEC40 LFEC1, LFEC3, LFEC6, LFECP6, LFECP10, LFECP15, LFECP20, LFECP33, LFECP40, LFEC10, LFEC15, LFEC20, LFEC33, LFEC40, 6 3-3 DC and Switching Characteristics LatticeECP/EC Family Data Sheet 5 Typ. Max. 100 GND. ...
Page 40
... LFECP10/LFEC10 LFECP15/LFEC15 LFECP20/LFEC20 LFECP33/LFEC33 LFECP40/LFEC40 LFEC1 LFEC3 LFECP6/LFECP6 LFECP10/LFEC10 LFECP15/LFEC15 LFECP20/LFEC20 LFECP33/LFEC33 LFECP40/LFEC40 LFEC1, LFEC3, LFEC6, LFECP6, LFECP10, LFECP15, LFECP20, LFECP33, LFECP40, LFEC10, LFEC15, LFEC20, LFEC33, LFEC40, 7 3-4 DC and Switching Characteristics LatticeECP/EC Family Data Sheet 6 Typ. Max. 150 GND. ...
Page 41
... Lattice Semiconductor sysIO Recommended Operating Conditions Standard Min. LVCMOS 3.3 3.135 LVCMOS 2.5 2.375 LVCMOS 1.8 1.71 LVCMOS 1.5 1.425 LVCMOS 1.2 1.14 LVTTL 3.135 PCI 3.135 SSTL18 Class I 1.71 SSTL2 Class I, II 2.375 SSTL3 Class I, II 3.135 HSTL15 Class I 1.425 HSTL15 Class III 1.425 HSTL 18 Class I, II 1.71 HSTL 18 Class III 1 ...
Page 42
... Lattice Semiconductor sysIO Single-Ended DC Electrical Characteristics V IL Input/Output Standard Min. (V) Max. (V) LVCMOS 3.3 -0.3 0.8 LVTTL -0.3 0.8 LVCMOS 2.5 -0.3 0.7 LVCMOS 1.8 -0.3 0.35V CCIO LVCMOS 1.5 -0.3 0.35V CCIO LVCMOS 1.2 -0.3 0.35V PCI -0.3 0.3V CCIO SSTL3 class I -0 0.2 REF SSTL3 class II -0 0.2 REF SSTL2 class I -0 0.18 REF SSTL2 class II -0 0.18 REF SSTL18 class I -0 ...
Page 43
... Lattice Semiconductor sysIO Differential Electrical Characteristics LVDS Parameter Symbol Parameter Description V V Input voltage INP, INM V Differential input threshold THD V Input common mode voltage CM I Input current IN V Output high voltage for Output low voltage for Output voltage differential ...
Page 44
... Lattice Semiconductor Differential HSTL and SSTL Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allow- able single-ended output classes (class I and class II) are supported in this mode. BLVDS The LatticeECP/EC devices support BLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs ...
Page 45
... Lattice Semiconductor LVPECL The LatticeECP/EC devices support differential LVPECL standard. This standard is emulated using complemen- tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-2 is one possible solution for point-to-point signals. Figure 3-2. Differential LVPECL 3.3V 3.3V Table 3-2. LVPECL DC Conditions ...
Page 46
... Lattice Semiconductor RSDS The LatticeECP/EC devices support differential RSDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-3 is one possible solution for RSDS standard implementation. Use LVDS25E mode with suggested resistors for RSDS operation ...
Page 47
... Lattice Semiconductor Figure 3-5. Typical PCI Clamp Current 400 350 300 250 200 150 100 Voltage (V) 3-11 DC and Switching Characteristics LatticeECP/EC Family Data Sheet ...
Page 48
... Lattice Semiconductor Typical Building Block Function Performance Pin-to-Pin Performance (LVCMOS25 12mA Drive) Function Basic Functions 16 bit decoder 32 bit decoder 64 bit decoder 4:1 MUX 8:1 MUX 16:1 MUX 32:1 MUX Combinatorial (pin to LUT to pin) Register-to-Register Performance Function Basic Functions 16 bit decoder 32 bit decoder 64 bit decoder ...
Page 49
... Lattice Semiconductor Derating Timing Tables Logic Timing provided in the following sections of the data sheet and the ispLEVER design tools are worst-case numbers in the operating range. Actual delays at nominal temperature and voltage for best-case process, can be much better than the values given in the tables. To calculate logic timing numbers at a particular temperature and voltage multiply the noted numbers with the derating factors provided below ...
Page 50
... Lattice Semiconductor LatticeECP/EC External Switching Characteristics Parameter Description General I/O Pin Parameters (Using Primary Clock without PLL) t Clock to Output - PIO Output Register CO t Clock to Data Setup - PIO Input Register SU t Clock to Data Hold - PIO Input Register H Clock to Data Setup - PIO Input Register ...
Page 51
... Lattice Semiconductor LatticeECP/EC Internal Timing Parameters Parameter Description PFU/PFF Logic Mode Timing t LUT4 delay ( inputs to F output) LUT4_PFU t LUT6 delay ( inputs to OFX output) LUT6_PFU t Set/Reset to output of PFU LSR_PFU t Clock to Mux (M0,M1) input setup time SUM_PFU t Clock to Mux (M0,M1) input hold time ...
Page 52
... Lattice Semiconductor LatticeECP/EC Internal Timing Parameters Parameter Description t Hold Write/Read Enable to PFU Memory HWREN_EBR Clock Enable Setup Time to EBR Output t SUCE_EBR Register Clock Enable Hold Time to EBR Output t HCE_EBR Register Reset To Output Delay Time from EBR Out- t RSTO_EBR put Register PLL Parameters ...
Page 53
... Lattice Semiconductor Timing Diagrams PFU Timing Diagrams Figure 3-7. Slice Single/Dual Port Write Cycle Timing Figure 3-8. Slice Single /Dual Port Read Cycle Timing WRE AD[3:0] DO[1:0] CK WRE AD[3: DI[1:0] DO[1:0] Old Data Old Data 3-17 DC and Switching Characteristics LatticeECP/EC Family Data Sheet ...
Page 54
... Lattice Semiconductor EBR Memory Timing Diagrams Figure 3-9. Read/Write Mode (Normal) CLKA CSA WEA ADA DIA D0 DOA Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. Figure 3-10. Read/Write Mode with Input and Output Registers ...
Page 55
... Lattice Semiconductor Figure 3-11. Read Before Write (SP Read/Write on Port A, Input Registers Only) CLKA CSA WEA ADA DIA DOA Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. ...
Page 56
... Lattice Semiconductor LatticeECP/EC Family Timing Adders Buffer Type Input Adjusters LVDS25 LVDS BLVDS25 BLVDS LVPECL33 LVPECL HSTL18_I HSTL_18 class I HSTL18_II HSTL_18 class II HSTL18_III HSTL_18 class III HSTL18D_I Differential HSTL 18 class I HSTL18D_II Differential HSTL 18 class II HSTL18D_III Differential HSTL 18 class III HSTL15_I HSTL_15 class I ...
Page 57
... Lattice Semiconductor LatticeECP/EC Family Timing Adders Buffer Type HSTL15_I HSTL_15 class I HSTL15_II HSTL_15 class II HSTL15_III HSTL_15 class III HSTL15D_I Differential HSTL 15 class I HSTL15D_III Differential HSTL 15 class III SSTL33_I SSTL_3 class I SSTL33_II SSTL_3 class II SSTL33D_I Differential SSTL_3 class I SSTL33D_II Differential SSTL_3 class II ...
Page 58
... Lattice Semiconductor sysCLOCK PLL Timing Parameter Descriptions f Input Clock Frequency (CLKI, CLKFB Output Clock Frequency (CLKOP, CLKOS) OUT f K-Divider Output Frequency (CLKOK) OUT2 f PLL VCO Frequency VCO f Phase Detector Input Frequency PFD AC Characteristics t Output Clock Duty Cycle Output Phase Accuracy ...
Page 59
... Lattice Semiconductor LatticeECP/EC sysCONFIG Port Timing Specifications Parameter sysCONFIG Byte Data Flow t Byte D[0:7] Setup Time to CCLK SUCBDI t Byte D[0:7] Hold Time to CCLK HCBDI t Clock to Dout in Flowthrough Mode CODO t CS[0:1] Setup Time to CCLK SUCS t CS[0:1] Hold Time to CCLK HCS t Write Signal Setup Time to CCLK ...
Page 60
... Lattice Semiconductor LatticeECP/EC sysCONFIG Port Timing Specifications (Continued) Parameter t SOSPI Data Setup Time Before CCLK SUSPI t SOSPI Data Hold Time After CCLK HSPI Master Clock Frequency Duty Cycle Rev F 0.18 Figure 3-13. sysCONFIG SPI Port Sequence Capture CFGx t ICFG VCC t PRGM PROGRAMN ...
Page 61
... Lattice Semiconductor JTAG Port Timing Specifications Symbol f TCK Clock Frequency MAX t TCK [BSCAN] clock pulse width BTCP t TCK [BSCAN] clock pulse width high BTCPH t TCK [BSCAN] clock pulse width low BTCPL t TCK [BSCAN] setup time BTS t TCK [BSCAN] hold time ...
Page 62
... Lattice Semiconductor Switching Test Conditions Figure 3-14 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 3-5. Figure 3-14. Output Test Load, LVTTL and LVCMOS Standards Table 3-5. Test Fixture Required Components, Non-Terminated Interfaces Test Condition LVTTL and other LVCMOS settings (L -> ...
Page 63
... TMS TCK © 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 64
... Lattice Semiconductor Signal Descriptions (Cont.) Signal Name TDI TDO V CCJ Configuration Pads (used during sysCONFIG) CFG[2:0] INITN PROGRAMN DONE CCLK BUSY/SISPI CSN CS1N WRITEN D[7:0]/SPID[0:7] DOUT/CSON DI/CSSPIN LatticeECP/EC Family Data Sheet I/O Test Data in pin. Used to load data into device using 1149.1 state machine. ...
Page 65
... Lattice Semiconductor PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin PICs Associated with DQS Strobe P[Edge] [n-4] P[Edge] [n-3] P[Edge] [n-2] P[Edge] [n-1] P[Edge] [n] P[Edge] [n+1] P[Edge] [n+2] P[Edge] [n+3] Notes: 1. “n” Row/Column PIC number 2. The DDR interface is designed for memories that support one DQS strobe per eight bits of data. In some packages, all the potential DDR data (DQ) pins may not be available. 3. PIC numbering defi ...
Page 66
... Lattice Semiconductor Pin Information Summary Pin Type Single Ended User I/O Differential Pair User I/O Dedicated Configuration Muxed TAP Dedicated (total without supplies CCAUX Bank0 Bank1 Bank2 Bank3 V CCIO Bank4 Bank5 Bank6 Bank7 GND, GND0-GND7 NC Bank0 Bank1 Bank2 Single Ended/ Bank3 ...
Page 67
... Lattice Semiconductor Power Supply and NC Connections Signals VCC 11, 13, 92, 99 VCCIO0 136, 143 VCCIO1 110, 125 VCCIO2 108 VCCIO3 73, 84 VCCIO4 55, 71 VCCIO5 38, 44 VCCIO6 24, 36 VCCIO7 1 VCCJ 19 VCCAUX 54, 126 GND, GND0-GND7 12, 15, 28, 37, 52, 63, 72, 80, 96, 98, 109, 117, 128, 144 ...
Page 68
... Lattice Semiconductor Power Supply and NC Connections Signals VCC VCCIO0 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCJ VCCAUX GND, GND0-GND7 NC LatticeECP/EC Family Data Sheet 484 fpBGA J6, J7, J16, J17, K6, K7, K16, K17, L6, L17, M6, M17, N6, N7, N16, N17, P6, P7, P16, P17 G11, H9, H10, H11 ...
Page 69
... Lattice Semiconductor LFECP6/LFEC6 Logic Signal Connections: 144 TQFP Pin Number Pin Function 1 VCCIO7 2 PL2A 3 PL2B 4 PL7A 5 PL7B 6 PL8A 7 PL8B 8 PL9A 9 PL9B 10 XRES 11 12 GND GND VCCJ 20 PL20A 21 PL20B 22 PL21A 23 PL21B 24 VCCIO6 25 PL22A 26 PL22B 27 PL23A 28 GND6 29 PL23B 30 PL24A 31 PL24B ...
Page 70
... Lattice Semiconductor LFECP6/LFEC6 Logic Signal Connections: 144 TQFP (Cont.) Pin Number Pin Function 44 VCCIO5 45 PB14A 46 PB14B 47 PB15A 48 PB15B 49 PB16A 50 PB16B 51 PB17A 52 GND5 53 PB17B 54 VCCAUX 55 VCCIO4 56 PB18A 57 PB18B 58 PB19A 59 PB19B 60 PB20A 61 PB20B 62 PB21A 63 GND4 64 PB21B 65 PB22A 66 PB22B 67 PB23A 68 PB23B 69 PB24B 70 PB25B 71 VCCIO4 ...
Page 71
... Lattice Semiconductor LFECP6/LFEC6 Logic Signal Connections: 144 TQFP (Cont.) Pin Number Pin Function 88 PR20A 89 CFG2 90 CFG1 91 CFG0 92 VCC 93 PROGRAMN 94 CCLK 95 INITN 96 GND 97 DONE 98 GND 99 VCC 100 PR9B 101 PR9A 102 PR8B 103 PR8A 104 PR7B 105 PR7A 106 PR2B 107 PR2A ...
Page 72
... Lattice Semiconductor LFECP6/LFEC6 Logic Signal Connections: 144 TQFP (Cont.) Pin Number Pin Function 132 PT15B 133 PT15A 134 PT14B 135 PT14A 136 VCCIO0 137 PT13B 138 PT13A 139 PT12B 140 PT12A 141 PT10B 142 PT10A 143 VCCIO0 144* GND0, GND7 * Double bonded to the pin. ...
Page 73
... Lattice Semiconductor LFECP6/LFEC6 Logic Signal Connections: 208 PQFP Pin Number Pin Function 1* GND0, GND7 2 VCCIO7 3 PL2A 4 PL2B PL3B 8 PL4A 9 PL4B 10 PL5A 11 PL5B 12 PL6A 13 VCCIO7 14 PL6B 15 PL7A 16 PL7B 17 PL8A 18 GND7 19 PL8B 20 PL9A 21 PL9B 22 VCCAUX 23 XRES 24 25 GND GND ...
Page 74
... Lattice Semiconductor LFECP6/LFEC6 Logic Signal Connections: 208 PQFP (Cont.) Pin Number Pin Function 44 PL24B 45 PL25A 46 PL25B 47 PL26A 48 PL26B 49 PL27A 50 PL27B 51 VCCIO6 52* GND5, GND6 53 VCCIO5 54 PB2A 55 PB2B 56 PB3A 57 PB3B 58 PB4A 59 PB4B 60 PB5A 61 PB5B 62 PB6A 63 PB6B 64 VCCIO5 65 PB10A 66 PB10B 67 PB11A 68 PB11B 69 PB12A 70 PB12B ...
Page 75
... Lattice Semiconductor LFECP6/LFEC6 Logic Signal Connections: 208 PQFP (Cont.) Pin Number Pin Function 88 PB19A 89 PB19B 90 PB20A 91 PB20B 92 PB21A 93 GND4 94 PB21B 95 PB22A 96 PB22B 97 PB23A 98 PB23B 99 PB24A 100 PB24B 101 PB25A 102 PB25B 103 PB33A 104 VCCIO4 105* GND3, GND4 106 VCCIO3 107 ...
Page 76
... Lattice Semiconductor LFECP6/LFEC6 Logic Signal Connections: 208 PQFP (Cont.) Pin Number Pin Function 132 GND 133 DONE 134 GND 135 136 VCCAUX 137 PR9B 138 GND2 139 PR9A 140 PR8B 141 PR8A 142 PR7B 143 PR7A 144 PR6B 145 VCCIO2 146 ...
Page 77
... Lattice Semiconductor LFECP6/LFEC6 Logic Signal Connections: 208 PQFP (Cont.) Pin Number Pin Function 176 VCCIO1 177 VCCAUX 178 PT17B 179 GND0 180 PT17A 181 PT16B 182 PT16A 183 PT15B 184 PT15A 185 PT14B 186 PT14A 187 VCCIO0 188 PT13B 189 GND0 ...
Page 78
... Lattice Semiconductor LFECP6/LFEC6 Logic Signal Connections: 256 fpBGA Ball Number Ball Function GND GND7 D4 PL2A D3 PL2B C3 PL3A C2 PL3B B1 PL4A C1 PL4B E3 PL5A E4 PL5B F4 PL6A F5 PL6B G4 PL7A G3 PL7B D2 PL8A GND GND7 D1 PL8B E1 PL9A E2 PL9B F3 XRES G5 PL11A H5 PL11B F2 PL12A F1 PL12B H4 PL13A H3 PL13B G2 PL14A GND ...
Page 79
... Lattice Semiconductor LFECP6/LFEC6 Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Function K1 PL20B L2 PL21A L1 PL21B M2 PL22A M1 PL22B N1 PL23A GND GND6 N2 PL23B M4 PL24A M3 PL24B P1 PL25A R1 PL25B P2 PL26A P3 PL26B N3 PL27A N4 PL27B GND GND6 GND GND5 P4 PB2A N5 PB2B P5 PB3A P6 PB3B R4 PB4A R3 PB4B T2 PB5A ...
Page 80
... Lattice Semiconductor LFECP6/LFEC6 Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Function P8 PB14A N8 PB14B R9 PB15A R10 PB15B P9 PB16A N9 PB16B T10 PB17A GND GND5 T11 PB17B T12 PB18A T13 PB18B P10 PB19A N10 PB19B T14 PB20A T15 PB20B M10 PB21A GND ...
Page 81
... Lattice Semiconductor LFECP6/LFEC6 Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Function M16 PR21B L16 PR21A K16 PR20B J16 PR20A L12 CFG2 L14 CFG1 L13 CFG0 K13 PROGRAMN L15 CCLK K15 INITN K14 DONE H16 PR18B GND GND3 H15 PR18A ...
Page 82
... Lattice Semiconductor LFECP6/LFEC6 Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Function D14 PR2B D13 PR2A GND GND2 GND GND1 GND GND1 B13 PT26B C13 PT26A GND GND1 C12 PT25B D12 PT25A A15 PT24B B14 PT24A D11 PT23B C11 PT23A ...
Page 83
... Lattice Semiconductor LFECP6/LFEC6 Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Function GND GND0 E6 PT9A D6 PT8B C6 PT8A B6 PT7B B5 PT7A A5 PT6B A4 PT6A A3 PT5B A2 PT5A B2 PT4B B3 PT4A D5 PT3B C5 PT3A C4 PT2B B4 PT2A GND GND0 A1 GND A16 GND G10 GND G7 GND G8 GND G9 GND H10 ...
Page 84
... Lattice Semiconductor LFECP6/LFEC6 Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Function R2 VCCAUX F7 VCCIO0 F8 VCCIO0 F10 VCCIO1 F9 VCCIO1 G11 VCCIO2 H11 VCCIO2 J11 VCCIO3 K11 VCCIO3 L10 VCCIO4 L9 VCCIO4 L7 VCCIO5 L8 VCCIO5 J6 VCCIO6 K6 VCCIO6 G6 VCCIO7 H6 VCCIO7 F6 F11 L11 L6 Bank - ...
Page 85
... Lattice Semiconductor LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA LFEC6/LFECP6 Ball Ball Number Function Bank LVDS GND GND7 7 D4 PL2A 7 E4 PL2B ...
Page 86
... Lattice Semiconductor LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA LFEC6/LFECP6 Ball Ball Number Function Bank LVDS J1 PL9A 7 GND GND7 7 K1 PL9B 7 L3 XRES 6 L4 PL11A 6 L5 PL11B 6 L2 PL12A 6 L1 PL12B 6 M4 PL13A 6 M5 PL13B 6 M1 PL14A 6 GND GND6 6 M2 PL14B ...
Page 87
... Lattice Semiconductor LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA LFEC6/LFECP6 Ball Ball Number Function Bank LVDS T4 TMS 6 U1 TDO 6 U2 VCCJ 6 V1 PL20A 6 V2 PL20B PL21A 6 V3 PL21B PL22A 6 V5 PL22B PL23A 6 GND GND6 6 W2 PL23B PL24A ...
Page 88
... Lattice Semiconductor LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA LFEC6/LFECP6 Ball Ball Number Function Bank LVDS AA3 AB3 AA5 AA4 AB4 PB2A 5 W8 PB2B PB3A 5 U8 PB3B PB4A 5 U9 PB4B ...
Page 89
... Lattice Semiconductor LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA LFEC6/LFECP6 Ball Ball Number Function Bank LVDS AA10 PB14A 5 AA9 PB14B 5 Y11 PB15A 5 AA11 PB15B 5 V11 PB16A 5 V12 PB16B 5 AB10 PB17A 5 GND GND5 5 AB11 PB17B 5 Y12 PB18A 4 U11 PB18B 4 W12 PB19A 4 U12 ...
Page 90
... Lattice Semiconductor LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA LFEC6/LFECP6 Ball Ball Number Function Bank LVDS AB19 PB33A AA18 PB33B 4 C W16 NC - U15 NC - V16 NC - U16 NC - Y17 NC - V17 NC - AB20 AA19 NC - Y16 NC - W17 NC - AA20 NC - Y19 NC - Y18 NC - W18 NC - T17 NC - U17 NC - GND GND4 4 GND GND3 ...
Page 91
... Lattice Semiconductor LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA LFEC6/LFECP6 Ball Ball Number Function Bank LVDS V18 PRO- 3 GRAMN T20 CCLK 3 T21 INITN 3 R20 DONE T18 NC - R17 NC - R19 NC - R18 NC - U22 T22 NC - R21 NC - R22 NC - P20 NC - N20 NC - P19 NC - P18 NC - P21 PR18B 3 C GND ...
Page 92
... Lattice Semiconductor LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA LFEC6/LFECP6 Ball Ball Number Function Bank LVDS GND GND2 2 J21 PR9A 2 H22 PR8B 2 C H21 PR8A 2 L19 PR7B 2 C L18 PR7A 2 K20 PR6B 2 C J20 PR6A 2 K19 PR5B K18 PR5A 2 G22 ...
Page 93
... Lattice Semiconductor LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA LFEC6/LFECP6 Ball Ball Number Function Bank LVDS D19 PR2A 2 GND GND2 2 GND GND1 1 G17 NC - F17 NC - D18 NC - C18 NC - C19 NC - B20 NC - D17 NC - C16 NC - B19 A20 NC - E17 NC - C17 NC - F16 NC - E16 NC - F15 NC - D16 NC - B18 PT33B ...
Page 94
... Lattice Semiconductor LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA LFEC6/LFECP6 Ball Ball Number Function Bank LVDS C13 PT24A 1 F14 PT23B 1 C D14 PT23A 1 E13 PT22B 1 C G13 PT22A 1 A12 PT21B 1 C GND GND1 1 B12 PT21A 1 F13 PT20B 1 C D13 PT20A 1 F12 ...
Page 95
... Lattice Semiconductor LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA LFEC6/LFECP6 Ball Ball Number Function Bank LVDS - - - C8 PT5A 0 F9 PT4B PT4A 0 F8 PT3B PT3A 0 D8 PT2B PT2A 0 GND GND0 ...
Page 96
... Lattice Semiconductor LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA LFEC6/LFECP6 Ball Ball Number Function Bank LVDS - - - A1 GND - A22 GND - AB1 GND - AB22 GND - H15 GND - H8 GND - J10 GND - J11 GND - J12 GND - J13 GND - J14 GND - J9 GND - K10 GND - K11 GND ...
Page 97
... Lattice Semiconductor LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA LFEC6/LFECP6 Ball Ball Number Function Bank LVDS P14 GND - P9 GND - R15 GND - R8 GND - J16 VCC - J7 VCC - K16 VCC - K17 VCC - K6 VCC - K7 VCC - L17 VCC - L6 VCC - M17 VCC - M6 VCC - N16 VCC - N17 VCC ...
Page 98
... Lattice Semiconductor LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA LFEC6/LFECP6 Ball Ball Number Function Bank LVDS R9 VCCIO5 5 T11 VCCIO5 5 M7 VCCIO6 6 M8 VCCIO6 6 N8 VCCIO6 6 P8 VCCIO6 6 J8 VCCIO7 7 K8 VCCIO7 7 L7 VCCIO7 7 L8 VCCIO7 7 G15 VCCAUX - G16 VCCAUX - G7 VCCAUX - G8 VCCAUX ...
Page 99
... Lattice Semiconductor LFECP20/LFEC20 Logic Signal Connections: 672 fpBGA Ball Number Ball Function E3 PL2A E4 PL2B B1 PL3A C1 PL3B F3 PL4A G3 PL4B D2 PL5A E2 PL5B D1 PL6A E1 PL6B F2 PL7A G2 PL7B F6 PL8A G6 PL8B H4 PL9A GND GND07 G4 PL9B J4 PL11A J5 PL11B K4 PL12A K5 PL12B J6 PL13A K6 PL13B F1 PL14A GND GND07 G1 PL14B H1 PL15A ...
Page 100
... Lattice Semiconductor LFECP20/LFEC20 Logic Signal Connections: 672 fpBGA (Cont.) Ball Number Ball Function N1 PL22B N3 XRES P1 PL24A P2 PL24B L7 PL25A L6 PL25B N4 PL26A N5 PL26B R1 PL27A GND GND06 R2 PL27B P4 PL28A P3 PL28B M5 PL29A M6 PL29B T1 PL30A T2 PL30B R4 PL31A GND GND06 R3 PL31B N6 PL32A P5 PL32B P6 PL33A R5 PL33B U1 PL34A U2 PL34B ...
Page 101
... Lattice Semiconductor LFECP20/LFEC20 Logic Signal Connections: 672 fpBGA (Cont.) Ball Number Ball Function W2 PL41B V6 PL42A W6 PL42B Y1 PL43A Y2 PL43B W3 PL44A GND GND06 W4 PL44B AA1 PL45A AB1 PL45B Y4 PL46A Y3 PL46B AC1 PL47A AB2 PL47B AB4 PL48A AC4 PL48B GND GND06 GND GND05 AB6 ...
Page 102
... Lattice Semiconductor LFECP20/LFEC20 Logic Signal Connections: 672 fpBGA (Cont.) Ball Number Ball Function AE5 PB14A AA9 PB14B AF5 PB15A Y10 PB15B AD6 PB16A AC10 PB16B AF6 PB17A GND GND05 AE6 PB17B AF7 PB18A AB10 PB18B AE7 PB19A AD10 PB19B AD7 PB20A ...
Page 103
... Lattice Semiconductor LFECP20/LFEC20 Logic Signal Connections: 672 fpBGA (Cont.) Ball Number Ball Function AE14 PB33B AA13 PB34A AB13 PB34B AD14 PB35A AA14 PB35B AC14 PB36A AB14 PB36B AF15 PB37A GND GND04 AE15 PB37B AD15 PB38A AC15 PB38B AF16 PB39A Y14 PB39B ...
Page 104
... Lattice Semiconductor LFECP20/LFEC20 Logic Signal Connections: 672 fpBGA (Cont.) Ball Number Ball Function GND GND04 AE20 PB53B AA19 PB54A Y18 PB54B AF23 PB55A AA20 PB55B AC18 PB56A AB18 PB56B AF24 PB57A AE23 PB57B GND GND04 GND GND03 AC23 PR48B AC24 PR48A ...
Page 105
... Lattice Semiconductor LFECP20/LFEC20 Logic Signal Connections: 672 fpBGA (Cont.) Ball Number Ball Function T21 PR36A T25 PR35B GND GND03 T26 PR35A T22 PR34B T23 PR34A T24 PR33B R23 PR33A R25 PR32B R24 PR32A R26 PR31B GND GND03 P26 PR31A R21 PR30B ...
Page 106
... Lattice Semiconductor LFECP20/LFEC20 Logic Signal Connections: 672 fpBGA (Cont.) Ball Number Ball Function J26 PR15B H26 PR15A H25 PR14B J24 PR14A GND GND02 K21 PR13B K22 PR13A K20 PR12B J20 PR12A K23 PR11B K24 PR11A F25 PR9B GND GND02 G25 PR9A ...
Page 107
... Lattice Semiconductor LFECP20/LFEC20 Logic Signal Connections: 672 fpBGA (Cont.) Ball Number Ball Function A21 PT51A E17 PT50B B17 PT50A C17 PT49B GND GND01 D17 PT49A F17 PT48B E20 PT48A G17 PT47B B20 PT47A E16 PT46B A20 PT46A A19 PT45B GND GND01 ...
Page 108
... Lattice Semiconductor LFECP20/LFEC20 Logic Signal Connections: 672 fpBGA (Cont.) Ball Number Ball Function A13 PT31B B13 PT31A F13 PT30B F12 PT30A A12 PT29B GND GND00 B12 PT29A A11 PT28B B11 PT28A D12 PT27B C12 PT27A B10 PT26B A10 PT26A G12 PT25B ...
Page 109
... Lattice Semiconductor LFECP20/LFEC20 Logic Signal Connections: 672 fpBGA (Cont.) Ball Number Ball Function B6 PT12A E9 PT11B C8 PT11A G8 PT10B B5 PT10A A3 PT9B GND GND00 A2 PT9A F8 PT8B B4 PT8A E8 PT7B B3 PT7A D8 PT6B G7 PT6A C4 PT5B C5 PT5A E7 PT4B D4 PT4A F7 PT3B D6 PT3A D7 PT2B E6 PT2A GND GND00 LatticeECP/EC Family Data Sheet ...
Page 110
... LFEC1E-3T100C 67 © 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com ...
Page 111
... Lattice Semiconductor Part Number I/Os LFEC1E-4T100C 67 LFEC1E-5T100C 67 Part Number I/Os LFEC3E-3F256C 160 LFEC3E-4F256C 160 LFEC3E-5F256C 160 LFEC3E-3Q208C 145 LFEC3E-4Q208C 145 LFEC3E-5Q208C 145 LFEC3E-3T144C 97 LFEC3E-4T144C 97 LFEC3E-5T144C 97 LFEC3E-3T100C 67 LFEC3E-4T100C 67 LFEC3E-5T100C 67 Part Number I/Os LFEC6E-3F484C 224 LFEC6E-4F484C 224 LFEC6E-5F484C 224 LFEC6E-3F256C 195 LFEC6E-4F256C 195 LFEC6E-5F256C 195 LFEC6E-3Q208C ...
Page 112
... Lattice Semiconductor Part Number I/Os LFEC15E-3F484C 352 LFEC15E-4F484C 352 LFEC15E-5F484C 352 LFEC15E-3F256C 195 LFEC15E-4F256C 195 LFEC15E-5F256C 195 Part Number I/Os LFEC20E-3F672C 400 LFEC20E-4F672C 400 LFEC20E-5F672C 400 LFEC20E-3F484C 360 LFEC20E-4F484C 360 LFEC20E-5F484C 360 Part Number I/Os LFEC33E-3F672C 496 LFEC33E-4F672C 496 LFEC33E-4F672C 496 LFEC33E-3F484C 360 LFEC33E-4F484C ...
Page 113
... LFECP20E-5F484C 360 Part Number I/Os LFECP33E-3F672C 496 LFECP33E-4F672C 496 LFECP33E-4F672C 496 LFECP33E-3F484C 360 LFECP33E-4F484C 360 LFECP33E-4F484C 360 Part Number I/Os LFECP40E-3F900C 576 LFECP40E-4F900C 576 LFECP40E-5F900C 576 LFECP40E-3F672C 496 LatticeECP Commercial (Continued) Grade Package -4 TQFP -5 TQFP Grade Package -3 fpBGA -4 fpBGA -5 fpBGA -3 fpBGA -4 fpBGA -5 fpBGA -3 ...
Page 114
... Lattice Semiconductor Part Number I/Os LFECP40E-4F672C 496 LFECP40E-5F672C 496 Part Number I/Os LFEC1E-3Q208I 112 LFEC1E-4Q208I 112 LFEC1E-3T144I 97 LFEC1E-4T144I 97 LFEC1E-3T100I 67 LFEC1E-4T100I 67 Part Number I/Os LFEC3E-3F256I 160 LFEC3E-4F256I 160 LFEC3E-3Q208I 145 LFEC3E-4Q208I 145 LFEC3E-3T144I 97 LFEC3E-4T144I 97 LFEC3E-3T100I 67 LFEC3E-4T100I 67 Part Number I/Os LFEC6E-3F484I 224 LFEC6E-4F484I 224 LFEC6E-3F256I 195 LFEC6E-4F256I ...
Page 115
... Lattice Semiconductor Part Number I/Os LFEC15E-3F256I 195 LFEC15E-4F256I 195 Part Number I/Os LFEC20E-3F672I 400 LFEC20E-4F672I 400 LFEC20E-3F484I 360 LFEC20E-4F484I 360 Part Number I/Os LFEC33-3F672I 496 LFEC33-4F672I 496 LFEC33-3F484I 360 LFEC33-4F484I 360 Part Number I/Os LFEC40E-3F900I 576 LFEC40E-4F900I 576 LFEC40E-3F672I 496 LFEC40E-4F672I 496 Part Number I/Os LFECP6E-3F484I ...
Page 116
... LFECP20E-4F484I 360 Part Number I/Os LFECP33-3F672I 496 LFECP33-4F672I 496 LFECP33-3F484I 360 LFECP33-4F484I 360 Part Number I/Os LFECP40E-3F900I 576 LFECP40E-4F900I 576 LFECP40E-3F672I 496 LFECP40E-4F672I 496 LatticeECP/EC Family Data Sheet LatticeECP Industrial (Continued) Grade Package -3 fpBGA -4 fpBGA -3 fpBGA -4 fpBGA Grade Package -3 fpBGA -4 fpBGA -3 fpBGA ...
Page 117
... PCI: ww.pcisig.com © 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...