LFECP40 Lattice Semiconductor, LFECP40 Datasheet - Page 23

• Manufacturer Part Number: LFECP40
• Description: (LFEC Series) LatticeECP/EC Family Data Sheet
• Manufacturer: Lattice Semiconductor

Lattice Semiconductor
Optimized DSP Functions
Lattice provides a library of optimized DSP IP functions. Some of the IPs planned for LatticeECP DSP are: Bit Cor-
relators, Fast Fourier Transform, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/ Decoder, Turbo
Encoder/Decoders and Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest list of available
DSP IPs.
Resources Available in the LatticeECP Family
Table 2-9 shows the maximum number of multipliers for each member of the LatticeECP family. Table 2-10 shows
the maximum available EBR RAM Blocks in each of the LatticeECP family. EBR blocks, together with Distributed
RAM can be used to store variables locally for the fast DSP operations.
Table 2-9. Number of DSP Blocks in LatticeECP Family
Table 2-10. Embedded SRAM in LatticeECP Family
DSP Performance of the LatticeECP Family
Table 2-11 lists the maximum performance in millions of MAC operations per second (MMAC) for each member of
the LatticeECP family.
Table 2-11. DSP Block Performance of LatticeECP Family
For further information on the sysDSP block, please see details of additional technical information at the end of this
data sheet.
LFECP10
LFECP15
LFECP20
LFECP33
LFECP40
LFECP6
Device
DSP Block
LFECP10
LFECP15
LFECP20
LFECP33
LFECP40
LFECP10
LFECP15
LFECP20
LFECP33
LFECP40
LFECP6
LFECP6
Device
Device
10
4
5
6
7
8
EBR SRAM Block
9x9 Multiplier
DSP Block
2-20
32
40
48
56
64
80
10
30
38
46
58
70
10
4
5
6
7
8
DSP Performance
Total EBR SRAM
18x18 Multiplier
LatticeECP/EC Family Data Sheet
(Kbits)
MMAC
3680
4600
5520
6440
7360
9200
276
350
424
535
645
16
20
24
28
32
40
92
36x36 Multiplier
10
4
5
6
7
8
Architecture