MT92220 Zarlink Semiconductor, MT92220 Datasheet - Page 127

• Manufacturer Part Number: MT92220
• Description: 1023 Channel Voice Over IP/AAL2 Processor
• Manufacturer: Zarlink Semiconductor

Data Sheet
The format of the RX AAL2 HDLC Channel Structure is the following:
Received Octet Count
A
B
HT
AR
RX HDLC Stream/Buffer
Index
HDLC Address
HDLC Control
Field
Field
+10
+12
+14
+A
+C
+E
+0
+2
+4
+6
+8
b 15
A
Last Packet Local Time Stamp [7:0]
Total number of bytes received on this channel so far. Every packet that gets to this
structure will be included. This field increments by the UDP Length - 8 each time
packet is received.
Clock Recovery channel A. When this field is set, an Adaptive Clock Recovery AAL2
Event Structure using this CPS packet’s UUI and LI fields will be written to the
Adaptive clock recovery queue A.
Clock Recovery channel B. When this field is set, an Adaptive Clock Recovery AAL2
Event Structure using this CPS packet’s UUI and LI fields will be written to the
Adaptive clock recovery queue B.
HDLC Encapsulation type. ‘0’ = HDLC Bit-wise; ‘1’ = HDLC Byte-wise.
Always Report Enable. Always generate an RX Disassembly Event Report Structure
when a packet is received and this field is set. Used for debugging only.
Index in the RX HDLC Stream/Buffer Control Table in SSRAM B.
Field that may be inserted in the HDLC packet header, depending on the Header
Type.
Field that may be inserted in the HDLC packet, depending on the Header Type.
b14
B
Table 50 - Fields and Description (continued)
b13
HT
Figure 66 - RX AAL2 HDLC Channel Structure
b12
0
Table 51 - Fields and Description
b11
AR
Last Packet Local Time Stamp [23:8]
Received Packet Count [15:0]
Received Octet Count [31:16]
b10
Zarlink Semiconductor Inc.
Received Octet Count [15:0]
Maximum Bucket Fill [15:0]
Current Bucket Fill [15:0]
HDLC Address [15:0]
b9
0
Discharge Rate [5:0]
b8
0
RX HDLC Stream/Buffer Index [8:0]
b7
I
Description
Description
b6
HDLC Control [7:0]
b5
Current Bucket Fill [21:16]
b4
Header Type
b3
b2
b1
CRC
b0
MT92220
127