MT92220 Zarlink Semiconductor, MT92220 Datasheet - Page 35

• Manufacturer Part Number: MT92220
• Description: 1023 Channel Voice Over IP/AAL2 Processor
• Manufacturer: Zarlink Semiconductor

Data Sheet
Normal Cell Route
OAM Cell Route
AAL2 / AAL5 VC Struct
Base
+0
b31
b30
Field
b29
Normal Cell Route
Indexing within the UTOPIA LUT is done using programmable VPI/VCI bits. See
registers 420h to 42Ah and 440h to 44Ah.
N is a 2^n number between 1024 and 65536.
The base address starts on a boundary equal to the size of the LUT.
The LUT is located in SSRAM C.
b28
b27
b26
b25
b24
“xxxxxxxx1” = TX Link A Raw Cell Buffer 0;
“xxxxxx1” = TX Link A Raw Cell Buffer 0;
“xxxxx1x” = TX Link A Raw Cell Buffer 1;
“xxxx1xx” = TX Link A Raw Cell Buffer 2;
“xxx1xxx” = TX Link A Raw Cell Buffer 3;
“xx1xxxx” = TX Link B Raw Cell Buffer 0;
“x1xxxxx” = TX Link B Raw Cell Buffer 1;
“1xxxxxx” = RX CPU Raw Cell Buffer;
When a VC’s Normal Cell Route indicates that its cell should be sent to the Packet
Reassembly module (for AAL5 reassembly), In AAL5, this points to a Packet
Reassembly structure. In AAL2, this points to an RX AAL2 VC structure.
b23
“xxxxxxx1x” = TX Link A Raw Cell Buffer 1;
“xxxxxx1xx” = TX Link A Raw Cell Buffer 2;
“xxxxx1xxx” = TX Link A Raw Cell Buffer 3;
“xxxx1xxxx” = TX Link B Raw Cell Buffer 0;
“xxx1xxxxx” = TX Link B Raw Cell Buffer 1;
“xx1xxxxxx” = RX CPU Raw Cell Buffer;
“x1xxxxxxx” = RX AAL2 Raw Cell Bufferreserved;
“100000000” = AAL5 VC;
b22
+(N-2)*4
+(N-1)*4
b21
Figure 13 - UTOPIA LUT Entry Format
Table 11 - Fields and Description
OAM Cell Route
Figure 12 - UTOPIA Look Up Table
b20
+0
+4
b19
Zarlink Semiconductor Inc.
b18
b17
b16
LUT Entry N-2
LUT Entry N-1
LUT Entry 0
LUT Entry 1
b15
b14
b13
b12
Description
AAL2 / AAL5 VC Struct Base [20:5]
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
MT92220
b0
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