MT92220 Zarlink Semiconductor, MT92220 Datasheet - Page 75

• Manufacturer Part Number: MT92220
• Description: 1023 Channel Voice Over IP/AAL2 Processor
• Manufacturer: Zarlink Semiconductor

Data Sheet
Assembly Structure Base
Address
CPU Packet Base
Address
TI
TDM Write Pointer
Buf Size
CPU Packet Length
Time Stamp
CPS Timer
Assembly Structure Base
Address
CPU Packet Base
Address
FL
Field
Field
+C
+A
+E
+0
+2
+4
+6
+8
b 15
0
0
b14
FL
0
Base address of the Tx RTP Connection Structure to which this event is being sent.
The base address is pointed to in increments of 64 bytes.
Pointer to the first byte of the CPU packet in external memory. This pointer points to
32-byte increments in SSRAM A.
Time Stamp Insert. When ‘0’, the time stamp will be inserted in the packet as it is
received in the CPU packet. When ‘1’, the time stamp in the CPU packet will be
treated as an offset from the current bus time-stamp.
TDM Write Pointer used to write xxPCM samples in the TX Circular Buffers at the
time of the generation of this event.
Size of the CPU circular buffer in which the CPU packet is contained.
Length of the payload of the CPU packet in bytes.
Local Bus Time Stamp during which the CPU packet was queued.
Figure 43 - Assembly Event - Send CPU AAL2 Packet
CPS Timer to be applied to this packet when it is pending transmission due to an
incomplete cell. Units are in frames.
Base address of the Tx AAL2 Connection Structure to which this event is being
sent. The base address is pointed to in increments of 64 bytes.
Pointer to the first byte of the CPU packet in external memory. This pointer points
to 32 byte increments in SSRAM A.
Flush Pending Packet. When ‘1’, pending packets will be sent in a zero padded
cell before this packet is sent. When ‘0’, normal TX CPS processing will be done
to try to maximize bandwidth utilization.
b13
1
Buf Size
Assembly Structure Base Address [20:6]
b12
0
Table 31 - Fields and Description
Table 32 - Fields and Description
b11
CPU Packet Base Address [20:5]
b10
Zarlink Semiconductor Inc.
TX AAL2 VC Base [20:5]
b9
TDM Write Pointer [13:0]
b8
CPU Packet Length [10:0]
b7
CPS Timer [11:0]
b6
Description
Description
b5
CID [7:0]
b4
b3
b2
b1
b0
MT92220
75