MPC5554 Motorola, MPC5554 Datasheet
MPC5554
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MPC5554 Summary of contents
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... Freescale Semiconductor Product Brief MPC5554 Microcontroller Product Brief The MPC5554 is the first member of a family of next generation microcontrollers based on the PowerPC™ Book E architecture that enhances the PowerPC architecture’s fit in embedded applications 100% user mode compatible (with floating point library) with the classic PowerPC instruction set ...
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... Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard • Device/board test support per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) To locate any published errata or updates for this document, refer to the web site at http://www.freescale.com. 2 MPC5554 Microcontroller Product Brief, Rev. 2.1 Freescale Semiconductor ...
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... Block Diagram Figure 1 shows a top-level block diagram of the MPC5554. e200z6 Core 1.5V Regulator Processing Control Execution FMPLL Nexus Interface eDMA 64 channels Master Slave Flash 2Mbyte System/Bus Integration Peripheral Bridge A (PBRIDGE_A) 3K Data eTPU RAM 32 16K Code channel RAM MPC5500 Device Module Acronyms CAN – ...
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... Features 2 Features This section provides a high-level description of the major features of the MPC5554. • High performance e200z6 core processor — 32-bit PowerPC Book E compliant CPU — 32 64-bit general-purpose registers (GPRs) — Memory management unit (MMU) with 32-entry, fully-associative translation look-aside buffer (TLB) — ...
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... Memory controller with support for various memory types — 32-bit data bus and 24-bit address bus with transfer size indication — Selectable drive strength — Configurable bus speed modes — Support for external master accesses to internal addresses — Burst support Freescale Semiconductor MPC5554 Microcontroller Product Brief, Rev. 2.1 Features 5 ...
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... PWM, and modulus counter functionality — Supports all DASM and PWM modes of MIOS14 (MPC5xx) — 4 selectable time bases plus shared time or angle counter bus — DMA and interrupt request support 6 MPC5554 Microcontroller Product Brief, Rev. 2.1 Freescale Semiconductor ...
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... Programmable frame size, baud rate, clock delay, and clock phase on a per frame basis – Modified SPI mode for interfacing to peripherals with longer setup time requirements — Deserial serial interface (DSI) – Pin reduction by hardware serialization and deserialization of eTPU and eMIOS channels Freescale Semiconductor MPC5554 Microcontroller Product Brief, Rev. 2.1 Features 7 ...
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... JTAGC/debug or normal system operation. — A 5-bit instruction register that supports IEEE® 1149.1-2001 defined instructions — A 5-bit instruction register that supports additional public instructions — 3 test data registers: bypass, boundary scan, and device identification 8 MPC5554 Microcontroller Product Brief, Rev. 2.1 Freescale Semiconductor ...
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... POR block — Provides initial reset condition up to the voltage at which pins (RESET) can be read safely. It does not guarantee the safe operation of the chip at specified minimum operating voltages. Freescale Semiconductor MPC5554 Microcontroller Product Brief, Rev. 2.1 Features 9 ...
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... THIS PAGE INTENTIONALLY LEFT BLANK Freescale Semiconductor MPC5554 Microcontroller Product Brief, Rev. 2.1 11 ...
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... Semiconductor, Inc. All other product or service names are the property of their respective owners. The described product contains a PowerPC processor core. The PowerPC name is a trademark of IBM Corp. and used under license. © Freescale Semiconductor, Inc. 2005. All rights reserved. MPC5554PB Rev. 2.1 06/2005 ...