MPC5554 Motorola, MPC5554 Datasheet - Page 7

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MPC5554

Manufacturer Part Number
MPC5554
Description
Microcontroller
Manufacturer
Motorola
Datasheet

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— Motor control capability
Enhanced time processor unit (eTPU)
— MPC5554 has 2 eTPU engines
— Each eTPU engine is an event-triggered timer subsystem
— High level assembler/compiler
— 32 channels per engine
— 24-bit timer resolution
— 16-Kbyte shared code memory
— 3-Kbyte shared data memory
— Variable number of parameters allocatable per channel
— Double match/capture channels
— Angle clock hardware support
— Shared time or angle counter bus for all eTPU and eMIOS modules
— DMA and interrupt request support
— Nexus Class 3 Debug support (with some Class 4 support)
Enhanced queued analog/digital converter (eQADC)
— 2 independent ADCs with 12-bit A/D resolution
— Common mode conversion range of 0–5V
— 40 single-ended inputs channels, expandable to 65 channels with external multiplexers
— 4 pairs of differential analog input channels.
— 10-bit accuracy at 400 ksamples/s, 8-bit accuracy at 800 ksamples/s
— Supports 6 FIFO queues with fixed priority.
— Queue modes with priority-based preemption; initiated by software command, internal (eTPU
— DMA and interrupt request support
— Supports all functional modes from QADC (MPC5xx family)
4 Deserial serial peripheral interface modules (DSPI)
— Serial peripheral interface (SPI)
— Deserial serial interface (DSI)
and eMIOS), or external triggers
– Full duplex communication ports with interrupt and eDMA request support
– Supports all functional modes from QSPI submodule of QSMCM (MPC5xx family)
– Support for queues in RAM
– 6 chip selects, expandable to 64 with external demultiplexers
– Programmable frame size, baud rate, clock delay, and clock phase on a per frame basis
– Modified SPI mode for interfacing to peripherals with longer setup time requirements
– Pin reduction by hardware serialization and deserialization of eTPU and eMIOS channels
MPC5554 Microcontroller Product Brief, Rev. 2.1
Features
7

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