PIC24H Microchip Technology, PIC24H Datasheet
PIC24H
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PIC24H Summary of contents
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... PIC24H 16-bit Microcontroller (MCU) families. This programming specification is required only for those developing programming support for the dsPIC33F/ PIC24H family. Customers only using one of these devices should use development tools that already provide support for device programming. This document includes programming specifications for the following devices: • ...
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... Section 5.0 “Device Programming – ICSP” describes the ICSP method. 2.1 Power Requirements All devices in the dsPIC33F/PIC24H family are dual volt- age supply designs: one supply for the core and another for the peripherals and I/O pins. A regulator is provided on-chip to alleviate the need for two external voltage supplies ...
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... PROGRAMMING SPECIFICATION 2.3 Pin Diagrams The pin diagrams for the dsPIC33F/PIC24H device family are shown in the following figures. The pins that are required for programming are listed in Table 2-1. The MCLR, PGC1, PGD1, PGC2, PGD2, PGC3 and PGD3 pins are shown in bold letters in the figures. ...
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... PROGRAMMING SPECIFICATION Pin Diagrams 64-Pin TQFP COFS/RG15 1 AN16/T2CK/T7CK/RC1 2 AN17/T3CK/T6CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/T5CK/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF DS70152D-page dsPIC33FJ64GP206 40 dsPIC33FJ128GP206 Preliminary www.DataSheet4U.com PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 64-Pin TQFP COFS/RG15 1 AN16/T2CK/T7CK/RC1 2 AN17/T3CK/T6CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/T5CK/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF © 2007 Microchip Technology Inc dsPIC33FJ64GP306 40 dsPIC33FJ128GP306 39 38 ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 64-Pin TQFP COFS/RG15 1 AN16/T2CK/T7CK/RC1 2 AN17/T3CK/T6CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/T5CK/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF DS70152D-page dsPIC33FJ256GP506 Preliminary www.DataSheet4U.com ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 64-Pin TQFP COFS/RG15 1 AN16/T2CK/T7CK/RC1 2 AN17/T3CK/T6CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/T5CK/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF © 2007 Microchip Technology Inc dsPIC33FJ64GP706 41 dsPIC33FJ128GP706 ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 80-Pin TQFP 1 COFS/RG15 AN16/T2CK/T7CK/RC1 2 3 AN17/T3CK/T6CK/RC2 4 AN18/T4CK/T9CK/RC3 5 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 6 SDI2/CN9/RG7 7 SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 TMS/AN20/INT1/RA12 13 TDO/AN21/INT2/RA13 14 AN5/CN7/RB5 15 AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC3/EMUC3/AN1/CN3/RB1 19 PGD3/EMUD3/AN0/CN2/RB0 20 DS70152D-page 8 dsPIC33FJ64GP708 dsPIC33FJ128GP708 Preliminary www.DataSheet4U.com PGC2/EMUC2/SOSCO/T1CK/ CN0/RC14 60 59 PGD2/EMUD2/SOSCI/CN1/RC13 58 OC1/RD0 IC4/RD11 ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 100-Pin TQFP COFS/RG15 AN29/RE5 4 AN30/RE6 AN31/RE7 5 AN16/T2CK/T7CK/RC1 6 AN17/T3CK/T6CK/RC2 7 AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/INT1/RA12 18 AN21/INT2/RA13 19 AN5/CN7/RB5 20 AN4/CN6/RB4 21 AN3/CN5/RB3 22 AN2/SS1/LVDIN/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 © 2007 Microchip Technology Inc. dsPIC33FJ64GP310 ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 100-Pin TQFP COFS/RG15 AN29/RE5 4 AN30/RE6 AN31/RE7 5 AN16/T2CK/T7CK/RC1 6 AN17/T3CK/T6CK/RC2 7 AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/INT1/RA12 18 AN21/INT2/RA13 19 AN5/CN7/RB5 20 AN4/CN6/RB4 21 AN3/CN5/RB3 22 AN2/SS1/LVDIN/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 DS70152D-page 10 dsPIC33FJ256GP510 Preliminary www.DataSheet4U.com PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 100-Pin TQFP COFS/RG15 AN29/RE5 4 AN30/RE6 AN31/RE7 5 AN16/T2CK/T7CK/RC1 6 AN17/T3CK/T6CK/RC2 7 AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/INT1/RA12 18 AN21/INT2/RA13 19 AN5/CN7/RB5 20 AN4/CN6/RB4 21 AN3/CN5/RB3 22 AN2/SS1/LVDIN/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 © 2007 Microchip Technology Inc. dsPIC33FJ64GP710 ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 64-Pin TQFP PWM3H/RE5 1 PWM4L/RE6 2 PWM4H/RE7 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/T5CK/CN11/RG9 AN5/QEB/IC8/CN7/RB5 11 AN4/QEA/IC7/CN6/RB4 12 AN3/INDX/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF DS70152D-page dsPIC33FJ64MC506 Preliminary www.DataSheet4U.com ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 64-Pin TQFP PWM3H/RE5 1 PWM4L/RE6 2 PWM4H/RE7 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/T5CK/CN11/RG9 AN5/QEB/IC8/CN7/RB5 11 AN4/QEA/IC7/CN6/RB4 12 AN3/INDX/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF © 2007 Microchip Technology Inc dsPIC33FJ128MC506 41 40 dsPIC33FJ64MC506 39 dsPIC33FJ128MC706 ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 80-Pin TQFP PWM3H/RE5 1 PWM4L/RE6 2 3 PWM4H/RE7 4 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 5 SCK2/CN8/RG6 6 SDI2/CN9/RG7 7 SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 TMS/FLTA/INT1/RE8 13 TDO/FLTB/INT2/RE9 14 AN5/QEB/CN7/RB5 15 AN4/QEA/CN6/RB4 16 AN3/INDX/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC3/EMUC3/AN1/CN3/RB1 19 PGD3/EMUD3/AN0/CN2/RB0 20 DS70152D-page 14 dsPIC33FJ64MC508 Preliminary www.DataSheet4U.com PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 60 PGD2/EMUD2/SOSCI/CN1/RC13 59 58 OC1/RD0 57 IC4/RD11 IC3/RD10 56 IC2/RD9 ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 80-Pin TQFP 1 PWM3H/RE5 PWM4L/RE6 2 3 PWM4H/RE7 4 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 5 SCK2/CN8/RG6 6 SDI2/CN9/RG7 7 SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 TMS/FLTA/INT1/RE8 13 TDO/FLTB/INT2/RE9 14 AN5/QEB/CN7/RB5 15 AN4/QEA/CN6/RB4 16 AN3/INDX/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC3/EMUC3/AN1/CN3/RB1 19 PGD3/EMUD3/AN0/CN2/RB0 20 © 2007 Microchip Technology Inc. dsPIC33FJ128MC708 Preliminary www.DataSheet4U.com 60 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13 59 58 ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 100-Pin TQFP COFS/RG15 PWM3H/RE5 4 PWM4L/RE6 5 PWM4H/RE7 AN16/T2CK/T7CK/RC1 6 AN17/T3CK/T6CK/RC2 7 AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/FLTA/INT1/RE8 18 AN21/FLTB/INT2/RE9 19 AN5/QEB/CN7/RB5 20 AN4/QEA/CN6/RB4 21 AN3/INDX/CN5/RB3 22 AN2/SS1/LVDIN/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 DS70152D-page 16 dsPIC33FJ64MC510 Preliminary www.DataSheet4U.com PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 100-Pin TQFP COFS/RG15 PWM3H/RE5 4 PWM4L/RE6 5 PWM4H/RE7 AN16/T2CK/T7CK/RC1 6 AN17/T3CK/T6CK/RC2 7 AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/FLTA/INT1/RE8 18 AN21/FLTB/INT2/RE9 19 AN5/QEB/CN7/RB5 20 AN4/QEA/CN6/RB4 21 AN3/INDX/CN5/RB3 22 AN2/SS1/LVDIN/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 © 2007 Microchip Technology Inc. dsPIC33FJ128MC510 ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 100-Pin TQFP COFS/RG15 PWM3H/RE5 4 PWM4L/RE6 5 PWM4H/RE7 AN16/T2CK/T7CK/RC1 6 AN17/T3CK/T6CK/RC2 7 AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/FLTA/INT1/RE8 18 AN21/FLTB/INT2/RE9 19 AN5/QEB/CN7/RB5 20 AN4/QEA/CN6/RB4 21 AN3/INDX/CN5/RB3 22 AN2/SS1/LVDIN/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 DS70152D-page 18 dsPIC33FJ64MC710 dsPIC33FJ128MC710 dsPIC33FJ256MC710 Preliminary www.DataSheet4U.com ...
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... AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF Note: The PIC24HJ64GP206 device does not have the SCL2 and SDA2 pins. © 2007 Microchip Technology Inc PIC24HJ64GP206 41 40 PIC24HJ128GP206 39 PIC24HJ256GP206 Preliminary www.DataSheet4U.com ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 64-Pin TQFP RG15 1 AN16/T2CK/T7CK/RC1 2 AN17/T3CK/T6CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/T5CK/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF DS70152D-page PIC24HJ128GP306 Preliminary www.DataSheet4U.com ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 64-Pin TQFP COFS/RG15 1 AN16/T2CK/T7CK/RC1 2 AN17/T3CK/T6CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/T5CK/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/CN4/RB2 14 PGC3/EMUC3/AN1/V -/CN3/RB1 15 REF PGD3/EMUD3/AN0/V +/CN2/RB0 16 REF © 2007 Microchip Technology Inc PIC24HJ64GP506 40 PIC24HJ128GP506 39 38 ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 100-Pin TQFP RG15 AN29/RE5 3 AN30/RE6 4 AN31/RE7 5 AN16/T2CK/T7CK/RC1 6 AN17/T3CK/T6CK/RC2 7 AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/INT1/RA12 18 AN21/INT2/RA13 19 20 AN5/CN7/RB5 AN4/CN6/RB4 21 AN3/CN5/RB3 22 AN2/SS1/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 DS70152D-page 22 PIC24HJ64GP210 PIC24HJ128GP210 PIC24HJ128GP310 PIC24HJ256GP210 Preliminary www ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 100-Pin TQFP 1 RG15 AN29/RE5 AN30/RE6 4 AN31/RE7 5 AN16/T2CK/T7CK/RC1 6 AN17/T3CK/T6CK/RC2 7 AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 10 SCK2/CN8/RG6 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 13 MCLR 14 SS2/CN11/RG9 TMS/RA0 17 AN20/INT1/RA12 18 AN21/INT2/RA13 19 AN5/CN7/RB5 20 AN4/CN6/RB4 21 22 AN3/CN5/RB3 AN2/SS1/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 25 PGD3/EMUD3/AN0/CN2/RB0 © 2007 Microchip Technology Inc. ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 100-Pin TQFP 1 RG15 AN29/RE5 3 AN30/RE6 4 AN31/RE7 5 AN16/T2CK/T7CK/RC1 6 AN17/T3CK/T6CK/RC2 7 AN18/T4CK/T9CK/RC3 8 AN19/T5CK/T8CK/RC4 9 SCK2/CN8/RG6 10 SDI2/CN9/RG7 11 SDO2/CN10/RG8 12 MCLR 13 SS2/CN11/RG9 TMS/RA0 17 AN20/INT1/RA12 18 AN21/INT2/RA13 19 AN5/CN7/RB5 20 AN4/CN6/RB4 21 AN3/CN5/RB3 22 AN2/SS1/CN4/RB2 23 PGC3/EMUC3/AN1/CN3/RB1 24 PGD3/EMUD3/AN0/CN2/RB0 25 DS70152D-page 24 PIC24HJ256GP610 Preliminary www.DataSheet4U.com PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 18-PIN SDIP 18-PIN SOIC PGD2/EMUD2/AN0/VREF+/CN2/RA0 PGC2/EMUC2/AN1/VREF-/CN3/RA1 PGD1/EMUD1/AN2/RP0/CN4/RB0 PGC1/EMUC1/AN3/RP1/CN5/RB1 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 PGD3/EMUD3/SOSCI/RP4/CN1/RB4 PGC3/EMUC3/SOSCO/T1CK/CN0/RA4 © 2007 Microchip Technology Inc MCLR AN6/RP15/CN11/RB15 AN7/RP14/CN12/RB14 DDCORE SCL1/RP9/CN21/RB9 SDA1/RP8/CN22/RB8 9 10 ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 20-PIN SDIP 20-PIN SSOP PGD2/EMUD2/AN0/VREF+/CN2/RA0 PGC2/EMC2/AN1/VREF-/CN3/RA1 PGD1/EMUD1/AN2/RP0/CN4/RB0 PGC1/EMUC1/AN3/RP1/CN5/RB1 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 PGD3/EMUD3/SOSCI/RP4/CN1/RB4 PGC3/EMUC3/SOSCO/T1CK/CN0/RA4 Pin Diagrams (Continued) 28-PIN SDIP 28-PIN SOIC PGD2/EMUD2/AN0/VREF+/CN2/RA0 PGC2/EMUC2/AN1/VREF-/CN3/RA1 PGD1/EMUD1/AN2/RP0/CN4/RB0 PGC1/EMUC1/AN3/RP1/CN5/RB1 OSCO/CLK1/CN30/RA2 OSCI/CLKI/CN29/RA3 PGD3/EMUD3/SOSC/RP4/CN1/RB4 PGC3/EMUC3/SOSCO/T1CK/CN0/RA4 ASDA1/RP5/CN27/RB5 DS70152D-page 26 MCLR ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 28-PIN SDIP 28-PIN SOIC PGD2/EMUD2/AN0/VREF+/CN2/RA0 PGC2/EMUC2/AN1/VREF-/CN3/RA1 PGD1/EMUD1/AN2/RP0/CN4/RB0 PGC1/EMUC1/AN3/RP1/CN5/RB1 AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 PGD3/EMUD3/SOSCI/RP4/CN1/RB4 PGC3/EMUC3/SOSCO/T1CK/CN0/RA4 ASDA1/RP5/CN27/RB5 © 2007 Microchip Technology Inc MCLR PWM1L1/RP15/CN11/RB15 4 25 PWM1H1/RP14/CN12/RB14 5 24 PWM1L2/RP13/CN13/RB13 6 23 PWM1H2/RP12/CN14/RB12 7 22 ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 28-Pin QFN 6*6mm PGD1/EMUD1/AN2/RP0/CN4/RB0 PGC1/EMUC1/AN3/RP1/CN5/RB1 AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 V SS OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 DS70152D-page dsPIC33FJ12GP202 4 PIC24HJ12GP202 Preliminary www.DataSheet4U.com AN8/RP13/CN13/RB13 21 AN9/RP12/CN14/RB12 20 19 TMS/RP11/CN15/RB11 18 TDI/RP10/CN16/RB10 V 17 DDCORE TDO/SDA1/RP9/CN21/RB9 15 © 2007 Microchip Technology Inc. ...
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... PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 28-Pin QFN 6*6mm PGD1/ EMUD1 /AN2/RP0/CN4/RB0 1 PGC1/ EMUC1 /AN3/RP1/CN5/RB1 2 AN4/RP2/CN6/RB2 3 AN5/RP3/CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 7 © 2007 Microchip Technology Inc dsPIC33FJ12MC202 Preliminary www.DataSheet4U.com PWM1L2/RP13/CN13/RB13 PWM1H2/RP12/CN14/RB12 ...
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... PROGRAMMING SPECIFICATION 2.4 Memory Map The program memory map extends from 0x0 to 0xFFFFFE. Code storage is located at the base of the memory map and supports up to 88K instructions (about 256 Kbytes). Table 2-2 shows the program memory size and number of erase and program blocks present in each device variant ...
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... PROGRAMMING SPECIFICATION TABLE 2-2: CODE MEMORY SIZE (CONTINUED) PIC24HJ128GP306 PIC24HJ128GP310 PIC24HJ128GP506 PIC24HJ128GP510 PIC24HJ256GP206 PIC24HJ256GP210 PIC24HJ256GP610 dsPIC33FJ12GP201 dsPIC33FJ12GP202 dsPIC33FJ12MC201 dsPIC33FJ12MC202 PIC24HJ12GP201 PIC24HJ12GP202 © 2007 Microchip Technology Inc. 0x0157FE (44K) 688 0x0157FE (44K) 688 0x0157FE (44K) 688 0x0157FE (44K) 688 0x02ABFE (88K) 1368 ...
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... PROGRAMMING SPECIFICATION FIGURE 2-3: PROGRAM MEMORY MAP Note: The address boundaries for user Flash and Executive code memory are device dependent. DS70152D-page 32 0x000000 User Flash Code Memory (87552 x 24-bit) 0x02ABFE 0x02AC00 Reserved 0x7FFFFE 0x800000 Executive Code Memory (2048 x 24-bit) 0x800FFE 0x801000 ...
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... Code Configuration registers) is then verified to ensure that programming was successful. After the programming executive has been verified in memory (or loaded if not present), the dsPIC33F/ PIC24H Programming Specification can be pro- grammed using the command set shown in Table 3-1. FIGURE 3-1: HIGH-LEVEL ENHANCED ICSP™ PROGRAMMING FLOW Enter Enhanced ICSP™ ...
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... MCLR is then driven high within a specified period of time and held. The programming voltage applied to MCLR is V which is essentially V DD PIC24H devices. There is no minimum time require- ment for holding After V IH val of at least P18 must elapse before presenting the key sequence on PGD ...
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... Next, one write block in the device is programmed with a PROGP command. Each PROGP command contains data for one row of code memory of the dsPIC33F/PIC24H. After the first command is processed successfully, ‘RemainingCmds’ is decremented by ‘1’ and compared with ‘ ...
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... No not included in the checksum computation. Table 3-2 shows how this 16-bit computation can be made for each dsPIC33F and PIC24H device. Compu- tations for read code protection are shown both enabled and disabled. The checksum values shown here assume that the Configuration registers are also erased ...
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... Byte sum of ((FBS & 0xCF) + (FSS & 0xFF) + (FGS & 0x07) + (FOSCSEL & 0xA7) + (FOSC & 0xE7) + (FWDT & 0xDF) + (FPOR & 0xE7) + (FICD & 0xE3)) (for dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202) = Byte sum of ((FBS & 0xCF) + (FSS & 0xCF) + (FGS & 0x07) + (FOSCSEL & 0xA7) + (FOSC & 0xC7) + (FWDT & ...
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... Byte sum of ((FBS & 0xCF) + (FSS & 0xFF) + (FGS & 0x07) + (FOSCSEL & 0xA7) + (FOSC & 0xE7) + (FWDT & 0xDF) + (FPOR & 0xE7) + (FICD & 0xE3)) (for dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202) = Byte sum of ((FBS & 0xCF) + (FSS & 0xCF) + (FGS & 0x07) + (FOSCSEL & 0xA7) + (FOSC & 0xC7) + (FWDT & ...
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... Byte sum of ((FBS & 0xCF) + (FSS & 0xFF) + (FGS & 0x07) + (FOSCSEL & 0xA7) + (FOSC & 0xE7) + (FWDT & 0xDF) + (FPOR & 0xE7) + (FICD & 0xE3)) (for dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202) = Byte sum of ((FBS & 0xCF) + (FSS & 0xCF) + (FGS & 0x07) + (FOSCSEL & 0xA7) + (FOSC & 0xC7) + (FWDT & ...
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... PROGRAMMING SPECIFICATION 3.6 Configuration Bits Programming 3.6.1 OVERVIEW The dsPIC33F/PIC24H has Configuration bits stored in twelve 8-bit Configuration registers, aligned on even configuration memory address boundaries. These bits can be set or cleared to select various device configu- rations. There are three types of Configuration bits: system operation bits, code-protect bits and unit ID bits. ...
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... PROGRAMMING SPECIFICATION TABLE 3-3: dsPIC33F/PIC24H CONFIGURATION BITS DESCRIPTION Bit Field Register RBS<1:0> FBS BSS<2:0> FBS BWRP FBS © 2007 Microchip Technology Inc. Description Boot Segment Data RAM Code Protection RAM is reserved for Boot Segment 10 = Small-sized Boot RAM [128 bytes of RAM are reserved for Boot Segment] ...
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... No Secure Segment 010 = High security, Small-sized Secure Program Flash [Secure Segment ends at 0x001FFF for dsPIC33FJ64GPxxx/ dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x003FFF in other devices.] 001 = High security, Medium-sized Secure Program Flash [Secure Segment ends at 0x003FFF for dsPIC33FJ64GPxxx/ dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x007FFF in other devices ...
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... Description General Segment Code-Protect bit 11 = Code protection is disabled 10 = Standard security code protection is enabled 0x = Reserved in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202. In all other devices, high security code protection is enabled. General Segment Write-Protect bit 1 = General Segment program memory is not write-protected 0 = General Segment program memory is write-protected ...
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... PROGRAMMING SPECIFICATION TABLE 3-3: dsPIC33F/PIC24H CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register WDTPOST FWDT PWMPIN FPOR HPOL FPOR LPOL FPOR ALTI2C FPOR FPWRT<2:0> FPOR BKBUG FICD COE FICD JTAGEN FICD ICS<1:0> FICD — All DS70152D-page 44 Description Watchdog Timer Postscaler bits 1111 = 1:32,768 1110 = 1:16,384 ...
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... These bits are only present in the dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 devices. In all other devices, they are unimplemented (read as ‘0’). 3: In the dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 devices, these bits are reserved (read as ‘1’ and must be programmed as ‘1’). ...
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... PGC and PGD before removing DS70152D-page 46 3.6.5 USER UNIT ID The dsPIC33F/PIC24H devices provide four 8-bit Con- figuration registers (FUID0 through FUID3) for the user to store product-specific information, such as unit serial numbers and other product manufacturing data. Start ConfigAddress = 0xF80000 Send PROGC ...
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... This protocol is shown in Figure 4-2. 4.1.2 SPI RATE In Enhanced ICSP mode, the dsPIC33F/PIC24H family devices operate from the Fast Internal RC oscillator, which has a nominal frequency of 7.3728 MHz. This oscillator frequency yields an effective system clock frequency of 1.8432 MHz. To ensure that the program- mer does not clock too fast recommended that a 7 ...
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... PROGRAMMING SPECIFICATION FIGURE 4-2: PROGRAMMING EXECUTIVE – PROGRAMMER COMMUNICATION PROTOCOL Host Transmits Last Command Word PGC PGD MSB LSB P8 PGC = Input PGD = Input 4.2 Programming Executive Commands The programming executive command set is shown in Table 4-1. This table contains the opcode, mnemonic, length, time out and description for each command ...
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... PROGRAMMING SPECIFICATION TABLE 4-1: PROGRAMMING EXECUTIVE COMMAND SET Length Opcode Mnemonic (16-bit words) 0x0 1 SCHECK 0x1 3 READC 0x2 4 READP 0x3 RESERVED N/A 0x4 4 PROGC 0x5 99 PROGP 0x6 5 PROGW 0x7 RESERVED N/A 0x8 RESERVED N/A 0x9 RESERVED N/A 0xA 2 QBLANK 0xB 1 QVER 0xC RESERVED N/A 0xD RESERVED ...
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... PROGRAMMING SPECIFICATION 4.2.6 READC COMMAND Opcode Length N Addr_MSB Addr_LS Field Description Opcode 0x1 Length 0x3 N Number of 8-bit Configuration registers or Device ID registers to read (max of 256) Addr_MSB MSB of 24-bit source address Addr_LS Least Significant 16 bits of 24-bit source address The READC command instructs the programming exec- ...
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... PROGRAMMING SPECIFICATION 4.2.8 PROGC COMMAND Opcode Length Reserved Addr_MSB Addr_LS Data Field Description Opcode 0x4 Length 0x4 Reserved 0x0 Addr_MSB MSB of 24-bit destination address Addr_LS Least Significant 16 bits of 24-bit destination address Data 8-bit data word The PROGC command instructs the programming exec- utive to program a single Configuration register, located at the specified memory address ...
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... PROGRAMMING SPECIFICATION 4.2.10 PROGW COMMAND Opcode Length Reserved Addr_MSB Addr_LS Data_LS Reserved Data_MSB Field Description Opcode 0x6 Length 0x5 Reserved 0x0 Addr_MSB MSB of 24-bit destination address Addr_LS Least Significant 16 bits of 24-bit destination address Data_MSB MSB of 24-bit data Data_LS Least Significant 16 bits of 24-bit ...
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... PROGRAMMING SPECIFICATION 4.2.12 QVER COMMAND Opcode Length Field Description Opcode 0xB Length 0x1 The QVER command queries the version of the programming executive software stored in test memory. The “version.revision” information is returned in the response’s QE_Code using a single byte with the following format: main version in upper nibble and revision in the lower nibble (i ...
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... PROGRAMMING SPECIFICATION 4.3.1.3 QE_Code Field The QE_Code is a byte in the first word of the response. This byte is used to return data for query commands and error codes for all other commands. When the programming executive processes one of the two query commands (QBLANK or QVER), the returned opcode is always PASS and the QE_Code holds the query response data ...
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... DEVICE PROGRAMMING – ICSP ICSP mode is a special programming protocol that allows you to read and write to dsPIC33F/PIC24H device family memory. The ICSP mode is the most direct method used to program the device; note, how- ever, that Enhanced ICSP is faster. ICSP mode also ...
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... SIX SERIAL INSTRUCTION EXECUTION The SIX control code allows execution of dsPIC33F/ PIC24H Programming Specification assembly instruc- tions. When the SIX code is received, the CPU is sus- pended for 24 clock cycles, as the instruction is then clocked into the internal buffer. Once the instruction is shifted in, the state machine allows executed over the next four clock cycles ...
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... MCLR is then driven high within a specified period of time and held. The programming voltage applied to MCLR is V which is essentially V in the case of dsPIC33F/ DD PIC24H devices. There is no minimum time require- ment for holding After V is removed, an inter val of at least P18 must elapse before presenting the key sequence on PGD ...
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... Before performing any segment erase operation, the programmer must first determine if the dsPIC33F/ PIC24H device has defined a Boot Segment or Secure Segment, and ensure that a segment does not get overwritten by operations on any other segment. Also, a Bulk Erase should not be performed if a Boot Segment or Secure Segment has been defined ...
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... PROGRAMMING SPECIFICATION TABLE 5-4: SERIAL INSTRUCTION EXECUTION FOR BULK ERASING CODE MEMORY Command Data (Binary) (Hex) Step 1: Exit the Reset vector. 0000 000000 NOP 0000 000000 NOP 0000 040200 GOTO 0000 000000 NOP Step 2: Set the NVMCON to erase all program memory. ...
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... PROGRAMMING SPECIFICATION TABLE 5-5: SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY Command Data (Binary) (Hex) Step 1: Exit the Reset vector. 0000 000000 NOP 0000 000000 NOP 0000 040200 GOTO 0000 000000 NOP Step 2: Set the NVMCON to program 64 instruction words. 0000 24001A ...
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... PROGRAMMING SPECIFICATION TABLE 5-5: SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY (CONTINUED) Command Data (Binary) (Hex Externally time ‘P13’ msec Characteristics and Timing Requirements”) to allow suffi- cient time for the Row Program operation to complete. 0000 807600 MOV 0000 887840 ...
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... PROGRAMMING SPECIFICATION 5.7 Writing Configuration Memory The 8-bit Configuration registers are programmable, one register at a time. The default programming values rec- ommended for the Configuration registers are shown in Table 5-6 and Table 5-7. The recommended default FOSCSEL value is 0x07, which selects the FRC clock oscillator setting ...
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... PROGRAMMING SPECIFICATION TABLE 5-8: SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION REGISTERS Command Data (Binary) (Hex) Step 1: Exit the Reset vector. 0000 000000 NOP 0000 000000 NOP 0000 040200 GOTO 0000 000000 NOP Step 2: Initialize the write pointer (W7) for the TBLWT instruction. ...
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... PROGRAMMING SPECIFICATION 5.8 Reading Code Memory Reading from code memory is performed by executing a series of TBLRD instructions and clocking out the data using the REGOUT command. Table 5-9 shows the ICSP programming details for reading code memory. In Step 1, the Reset vector is exited. In Step 2, the 24-bit starting source address for reading is loaded into the TBLPAG register and W6 register ...
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... PROGRAMMING SPECIFICATION 5.9 Reading Configuration Memory The procedure for reading configuration memory is similar to the procedure for reading code memory, except that 16-bit data words are read (with the upper byte read being all ‘0’s) instead of 24-bit words. Since there are twelve Configuration registers, they are read one register at a time ...
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... PROGRAMMING SPECIFICATION 5.10 Verify Code Memory and Configuration Word The verify step involves reading back the code memory space and comparing it against the copy held in the programmer’s buffer. The Configuration registers are verified with the rest of the code. The verify process is shown in the flowchart in Figure 5-8 ...
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... PROGRAMMING SPECIFICATION TABLE 5-11: SERIAL INSTRUCTION EXECUTION FOR READING THE APPLICATION ID WORD Command Data (Binary) (Hex) Step 1: Exit Reset vector. 0000 000000 NOP 0000 000000 NOP 0000 040200 GOTO 0000 000000 NOP Step 2: Initialize TBLPAG and the read pointer (W0) for TBLRD instruction. ...
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... PROGRAMMING SPECIFICATION 6.0 PROGRAMMING THE PROGRAMMING EXECUTIVE TO MEMORY 6.1 Overview determined that the programming executive is not present in executive memory (as described in Section 3.2 “Confirming the Presence of the Pro- gramming Executive”), it must be programmed into executive memory using ICSP, as described in Section 5.0 “Device Programming – ICSP”. ...
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... PROGRAMMING SPECIFICATION TABLE 6-1: PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED) Command Data (Binary) (Hex) Step 7: Load W0:W5 with the next 4 words of packed programming executive code and initialize W6 for programming. Programming starts from the base of executive memory (0x800000) using read pointer and write pointer. ...
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... PROGRAMMING SPECIFICATION TABLE 6-1: PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED) Command Data (Binary) (Hex) Step 12: Reset the device internal PC. 0000 040200 GOTO 0000 000000 NOP Step 13: Repeat Steps 7-12 until all 32 rows of executive memory have been programmed. DS70152D-page 70 Description 0x200 Preliminary www.DataSheet4U.com © 2007 Microchip Technology Inc. ...
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... PROGRAMMING SPECIFICATION 6.2 Programming Verification After the programming executive programmed to executive memory using ICSP, it must be verified. Verification is performed by reading out the contents of executive memory and comparing it with the image of the programming executive stored in the programmer. TABLE 6-2: READING EXECUTIVE MEMORY Command Data ...
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... PROGRAMMING SPECIFICATION 7.0 DEVICE ID The device ID region of memory can be used to determine mask, variant and information about the chip. The device ID region 16-bits and it can be read using the READC command. This region of memory is read-only and can also be read when code protection is enabled. ...
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... PROGRAMMING SPECIFICATION TABLE 7-2: dsPIC33F/PIC24H PROGRAMMING SPECIFICATION DEVICE ID REGISTERS Address Name 15 0xFF0000 DEVID 0xFF0002 DEVREV PROC<3:0> TABLE 7-3: DEVICE ID BITS DESCRIPTION Bit Field Register MASK<9:0> DEVID VARIANT<5:0> DEVID PROC<3:0> DEVREV REV<5:0> DEVREV DOT<5:0> DEVREV © 2007 Microchip Technology Inc. Bit ...
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... PROGRAMMING SPECIFICATION 8.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS Table 8-1 lists AC/DC characteristics and timing requirements. TABLE 8-1: AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS Standard Operating Conditions Operating Temperature: –40°C-85°C. Programming at 25°C is recommended. Param Symbol Characteristic No. D111 V Supply Voltage During Programming DD D112 I Programming Current on MCLR ...
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... PROGRAMMING SPECIFICATION TABLE 8-1: AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS (CONTINUED) Standard Operating Conditions Operating Temperature: –40°C-85°C. Programming at 25°C is recommended. Param Symbol Characteristic No. Delay from First MCLR ↓ to First PGC ↑ for P18 T 1 KEY Key Sequence on PGD Delay from Last PGC ↓ for Key Sequence ...
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... PROGRAMMING SPECIFICATION NOTES: DS70152D-page 76 Preliminary © 2007 Microchip Technology Inc. www.DataSheet4U.com ...
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... Added checksum computation equation Revision D (March 2007) • Added information specific to the dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/ 202 and PIC24HJ12GP201/202 devices in sev- eral sections, including pinout diagrams, program memory sizes and Device ID values • Added specific checksum computations for all dsPIC33F and PIC24H devices • ...
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... PROGRAMMING SPECIFICATION NOTES: DS70152D-page 78 Preliminary © 2007 Microchip Technology Inc. www.DataSheet4U.com ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U ...
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... Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Preliminary © 2007 Microchip Technology Inc. www.DataSheet4U.com EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris ...