PIC24H Microchip Technology, PIC24H Datasheet - Page 45

• Manufacturer Part Number: PIC24H
• Description: Flash Programming Specification
• Manufacturer: Microchip Technology

TABLE 3-4:
Note 1:
3.6.2
Configuration bits may be programmed a single byte at
a time using the PROGC command. This command
specifies the configuration data and Configuration
register
programmed, any unimplemented bits must be
programmed with a ‘0’ and any reserved bits must be
programmed with a ‘1’.
Twelve PROGC commands are required to program all
the Configuration bits. A flowchart for Configuration bit
programming is shown in Figure 3-5.
3.6.3
After the Configuration bits are programmed, the
contents of memory should be verified to ensure that
the programming was successful. Verification requires
the Configuration bits to be read back and compared
against the copy held in the programmer’s buffer. The
READC command reads back the programmed
Configuration bits and verifies that the programming
was successful.
Any unimplemented Configuration bits are read-only
and read as ‘0’. The reserved bits are read-only and
read as ‘1’.
© 2007 Microchip Technology Inc.
0xF8000E
0xF8000A
0xF8000C
0xF80000
0xF80002
0xF80004
0xF80006 FOSCSEL
0xF80008
0xF80010
0xF80012
0xF80014
0xF80016
Address
Note:
2:
3:
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
address.
On the dsPIC33F General Purpose Family devices (dsPIC33FJXXXGPXXX) and PIC24H devices, these
bits are reserved (read as ‘1’ and must be programmed as ‘1’).
These bits are only present in the dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and
PIC24HJ12GP201/202 devices. In all other devices, they are unimplemented (read as ‘0’).
In the dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 devices, these bits
are reserved (read as ‘1’ and must be programmed as ‘1’).
PROGRAMMING METHODOLOGY
If the General Code Segment Code-
Protect bit (GCP) is programmed to ‘0’,
code memory is code-protected and
can not be read. Code memory must
be verified before enabling read protec-
tion. See Section 3.6.4 “CodeGuard
Security Configuration Bits” for more
information about code-protect Configura-
tion bits.
PROGRAMMING VERIFICATION
FUID0
FUID1
FUID2
FUID3
FOSC
FWDT
FPOR
Name
FICD
FGS
FBS
FSS
dsPIC33F/PIC24H DEVICE CONFIGURATION REGISTER MAP
When
PWMPIN
FWDTEN
BKBUG
IESO
Bit 7
FCKSM<1:0>
Configuration
RBS<1:0>
RSS<1:0>
(1)
WINDIS
HPOL
Bit 6
(3)
(3)
COE
—
(1)
bits
IOL1WAY
JTAGEN
LPOL
Preliminary
are
TEMP
Bit 5
—
-
(1)
(2)
—
—
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
WDTPRE
ALTI2C
3.6.4
The FBS, FSS and FGS Configuration registers are
special Configuration registers that control the size and
level of code protection for the Boot Segment, Secure
Segment and General Segment, respectively. For each
segment, two main forms of code protection are
provided. One form prevents code memory from being
written (write protection), while the other prevents code
memory from being read (read protection).
BWRP, SWRP and GWRP bits control write protection
and BSS<2:0>, SSS<2:0> and GSS<1:0> bits controls
read protection. The Chip Erase ERASEB command
sets all the code protection bits to ‘1’, which allows the
device to be programmed.
When write protection is enabled, any programming
operation to code memory will fail. When read protec-
tion is enabled, any read from code memory will cause
a ‘0x0’ to be read, regardless of the actual contents of
code memory. Since the programming executive
always verifies what it programs, attempting to program
code memory with read protection enabled will also
result in failure.
It is imperative that all code protection bits are ‘1’ while
the device is being programmed and verified. Only after
the device is programmed and verified should any of
the above bits be programmed to ‘0’.
Bit 4
(2)
—
—
CODEGUARD SECURITY
CONFIGURATION BITS
Bit 3
—
—
SSS<2:0>
BSS<2:0>
OSCIOFNC
WDTPOST<3:0>
Bit 2
GSS<1:0>
www.DataSheet4U.com
(3)
FNOSC<2:0>
FPWRT<2:0>
DS70152D-page 45
Bit 1
POSCMD<1:0>
ICS<1:0>
SWRP
GWRP
BWRP
Bit 0
(3)