IDT5V9885B Integrated Device Technology, Inc., IDT5V9885B Datasheet - Page 20

• Manufacturer Part Number: IDT5V9885B
• Description: 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
• Manufacturer: Integrated Device Technology, Inc.

POWER UP AND POWER SAVING FEATURES
down of the chip, the PLLs must be powered down via the SUSPEND function or by setting the pre-scaler bits to '0x00' and disable the internal GINx signals
via the enable bits at memory address 0x05. Note that the register bits will not lose their state in the event of a chip power-down. The only possibility that the
register bits will lose their state is if the part was power-cycled. After coming out of shutdown mode, the PLLs will require time to relock.
JTAG pin and GINx being disabled via the GINENx bits. GIN5 will have an internal state of LOW. The GIN pins should be held LOW during power up to select
configuration0 as default. The output levels will be at an undefined state during power up.
(unless the output bank itself will not be used at all).
LOSS OF LOCK AND INPUT CLOCK
such failures. LOSS_LOCK signal will be asserted if any of the three powered up PLLs loses frequency lock for any event other than PLL shutdown. Lock
is determined by checking that the reference and feedback clocks are within 1/2 period of each other. LOSS_LOCK is also asserted for at least two clock cycles
of the newly selected clock when switching over to a different clock source (manual or automatic).
up on power up, the loss of the selected clock detection circuitry will reference an internal oscillator. LOSS_LOCK and LOSS_CLKIN cannot be used as reliable
inputs to other devices.
SWITCHOVER MODES
configuration bits, SM (0x34). The primary clock source can be programmed, via the PRIMCLK bit, to be either XTALIN/REFIN or CLKIN, which is determined
by the PRIMCLK bit. The other clock source input will be considered as the secondary source. This is more detailed in the 'REFERENCE CLOCK INPUT PINS
AND SELECTION'. Note that the switchover modes are asynchronous. If the reference clocks are directly routed to OUTx with no phase relationship, short
pulses can be generated during switchover. The automatic switchover mode will work only when the primary clock source is XTALIN/REFIN.
clock sources. As previously mentioned, the primary and secondary clock source setting is determined by the PRIMCLK bit. During the switchover, no glitches
will occur at the output of the device, although there may be frequency and phase drift, depending on the exact phase and frequency relationship between the
primary and secondary clocks. The LOSS_LOCK signal will be asserted for a minimum of two input clock cycles of the newly selected clock, even if the two inputs
are exactly in phase. GOUT1 is used as LOSS_CLKIN, which indicates the loss of the currently used selected clock.
functionalities. These two functions are determined by the SM bits being set to "10" for non-revertive and "11" for revertive.
LOSS_LOCK and LOSS_CLKIN signals will be asserted for a minimum of two secondary clock cycles. LOSS_LOCK will remain asserted until the PLL achieves
lock, as previously defined, to the new input clock. If there are no transitions on both clock sources, the LOSS_LOCK signal and LOSS_CLKIN signal will be
asserted. In this mode, once the secondary clock is selected, it will not automatically re-select the primary clock as the input clock, even if the secondary clock
goes away and the primary clock is functional. The CLK_SEL pin must be toggled to re-select the primary clock source as the input clock.
IDT5V9885B
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
If a global shutdown is enabled, SHUTDOWN pin asserted, most of the chip except for the PLLs will be powered down. In order to have a complete power
During power up, the values of GIN4, GIN3, GIN2, GIN1 and GIN0 will be latched and used for PLL configuration selection, regardless of the state of the I
The post-divider should never be disabled via PM bits after power up, or else it will render the output bank completely non-functional during normal operation,
During power up, the V
The device employs a loss of lock and loss of input clock detection circuitry. The GIN0/LOSS_LOCK and GIN1/LOSS_CLKIN are the outputs that indicate
The IDT5V9888 features redundant clock inputs which supports both Automatic and Manual switchover mode. These two modes are determined by the
MANUAL SWITCHOVER MODE
When SM[1:0] is "0x", the redundant inputs are in manual switchover mode. In this mode, CLK_SEL pin is used to switch between the primary and secondary
AUTOMATIC SWITCHOVER MODE
When SM[1:0] is "1x", the redundant inputs are in automatic switchover mode. Automatic switchover mode supports both revertive and non-revertive
Non-Revertive
The input clock selection will switch to the secondary clock source when there are no transitions on the primary clock source for two secondary clock cycles.
LOSS_CLKIN is asserted when the currently selected clock is lost or is asserted when both clocks are lost. In the event of the selected clock being absent
DD
ramp must be monotonic.
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INDUSTRIAL TEMPERATURE RANGE
2
C/